Hostname: page-component-586b7cd67f-vdxz6 Total loading time: 0 Render date: 2024-11-25T17:26:28.829Z Has data issue: false hasContentIssue false
  • English
  • Français

A Dual-Function UHV-Compatible Chamber for i) Low-Temperature Plasma-Assisted Oxidation, and ii) High-Temperature Rapid Thermal Processing of Si-Based Dielectric Gate Heterostructures

Published online by Cambridge University Press:  22 February 2011

S. Hattiangady ,
X-L Xu ,
M.J. Watkins ,
B. Hornung ,
V. Misra ,
G. Lucovsky  and
J.J. Wortman
S. Hattiangady
Affiliation:
Departments of Materials Science and Engineering, Electrical and Computer Engineering, and PhysicsNorth Carolina State University, Raleigh, NC 27695
X-L Xu
Affiliation:
Departments of Materials Science and Engineering, Electrical and Computer Engineering, and PhysicsNorth Carolina State University, Raleigh, NC 27695
M.J. Watkins
Affiliation:
Departments of Materials Science and Engineering, Electrical and Computer Engineering, and PhysicsNorth Carolina State University, Raleigh, NC 27695
B. Hornung
Affiliation:
Departments of Materials Science and Engineering, Electrical and Computer Engineering, and PhysicsNorth Carolina State University, Raleigh, NC 27695
V. Misra
Affiliation:
Departments of Materials Science and Engineering, Electrical and Computer Engineering, and PhysicsNorth Carolina State University, Raleigh, NC 27695
G. Lucovsky
Affiliation:
Departments of Materials Science and Engineering, Electrical and Computer Engineering, and PhysicsNorth Carolina State University, Raleigh, NC 27695
J.J. Wortman
Affiliation:
Departments of Materials Science and Engineering, Electrical and Computer Engineering, and PhysicsNorth Carolina State University, Raleigh, NC 27695
Get access

Abstract

A combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 300: Symposium D1 – III-V Electronic and Photonic Device Fabrication and Performance , 1993 , 581
Copyright
Copyright © Materials Research Society 1993

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Lo, G.Q., Ting, W.C., Shih, D.K., and Kwong, D.L., Appl. Phys. Lett. 56, 979 (1990).Google Scholar
2. Xu, X-L, Kuehn, R.T., Wortman, J.J. and Ozturk, M.C., Appl. Phys. Lett. 60, 3063 (1992).Google Scholar
3. Batey, J. and Tierney, E., J. Appl. Phys. 60, 3136 (1986).Google Scholar
4. Yasuda, T., Ma, Y., Habermehl, S., and Lucovsky, G., Appl. Phys. Lett. 60, 434 (1992).Google Scholar
5. Fountain, G.G., Rudder, R.A., Hattangady, S.V., Markunas, R.J., and Lindorme, P.S, J. Appl. Phys. 63, 4744 (1988).Google Scholar
6. Kern, W., Semiconductor International, 94 (1989).Google Scholar
7. Nicollian, E.H. and Brews, J.R., MOS Physics and Technology (John Wiley and Son, New York, 1982).Google Scholar