Hostname: page-component-78c5997874-j824f Total loading time: 0 Render date: 2024-11-19T04:33:33.097Z Has data issue: false hasContentIssue false
  • English
  • Français

Dopant Loss Origins of Low Energy Implanted Arsenic and Antimony for Ultra Shallow Junction Formation

Published online by Cambridge University Press:  10 February 2011

Kentaro Shibahara ,
Hiroaki Furumoto ,
Kazuhiko Egusa ,
Meishoku Koh  and
Shin Yokoyama
Kentaro Shibahara
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-hiroshima, 739-8527, Japan, [email protected]
Hiroaki Furumoto
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-hiroshima, 739-8527, Japan, [email protected]
Kazuhiko Egusa
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-hiroshima, 739-8527, Japan, [email protected]
Meishoku Koh
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-hiroshima, 739-8527, Japan, [email protected] The Japan Science and Technology Corporation, Higashi-hiroshima, Japan
Shin Yokoyama
Affiliation:
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-hiroshima, 739-8527, Japan, [email protected]
Get access

Abstract

We have investigated the origins of sheet resistance increase in ultra shallow junctions formed by low energy As or Sb implantation. The increase is mainly attributed to dopant loss during annealing due to pileup of dopant at Si02/Si interface. This problem is common to As and Sb and will become more significant as the implantation energies are decreased. We found that the pileup can be classified into two stages from the time dependence of Sb SIMS depth profile .In the early stage of annealing the pileup is very fast and is probably related to the transport of the dopants due to solid phase epitaxial growth of an amorphized layer formed by the implantation. In the later stage the pileup is much slower and is considered to be governed by dopant diffusion.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 532: Symposium EE – Silicon Front-End Technology - Materials Processing & Modeling , 1998 , 23
Copyright
Copyright © Materials Research Society 1998

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Takeuchi, K., Yamamoto, T., Furukawa, A., Tamura, T. and Yoshida, K., Symp. on VLSI Tech. Digest of Technical Papers, 9 (1995).Google Scholar
2. Hori, A., Nakaoka, H., Umimoto, H., Yamashita, K., Takase, M., Shimizu, N., Mizuno, B. and Odanaka, S., Tech. Digest Int. Electron Devices Meeting, 485 (1994).Google Scholar
3. Shibahara, K., Mifuji, M., Kawabata, K., Kugimiya, T., Furumoto, H., Tsuno, M., Yokoyama, S., Nagata, M., Miyazaki, S. and Hirose, M., Tech. Digest Int. Electron Devices Meeting, 579 (1996).Google Scholar
4. Sai-Halasz, G.A., Short, K.T. and Williams, J.S.., Electron Device Lett. EDL-6, 287 (1985).Google Scholar
5. Aoki, N., Kanemura, T. and Mizushima, I., Appl. Phys. Lett. 64, 3133 (1994).Google Scholar
6. Egusa, K. and Shibahara, K., to be presented at XIIth Int. Conf. on Ion Implantation Technology (1998).Google Scholar
7. Morehead, F.F., Crowder, B.L. and Title, R.S., J. Appl. Phys. 43, 1112 (1972).Google Scholar
8. Nakagawa, K., Miyao, M. andShiraki, Y., Jpn. J. App!. Phys. 27. L2013 (1988).Google Scholar