Hostname: page-component-77c89778f8-fv566 Total loading time: 0 Render date: 2024-07-17T10:39:16.202Z Has data issue: false hasContentIssue false
  • English
  • Français

Delamination Behavior of Cu-Low-k Stack Under Different Slurries

Published online by Cambridge University Press:  01 February 2011

A. K. Sikder ,
S. Thagella ,
P. B. Zantye  and
Ashok Kumar
A. K. Sikder
Affiliation:
Nanomaterials and Nanomanufacturing Research Center
S. Thagella
Affiliation:
Nanomaterials and Nanomanufacturing Research Center Department of Industrial Engineering
P. B. Zantye
Affiliation:
Nanomaterials and Nanomanufacturing Research Center Department of Mechanical Engineering, University of South Florida, Tampa, FL-33620
Ashok Kumar
Affiliation:
Nanomaterials and Nanomanufacturing Research Center Department of Mechanical Engineering, University of South Florida, Tampa, FL-33620
Get access

Abstract

Lower mechanical strength, reduced cohesive strength and lack of compatibility with other interconnect materials, are the major challenges involved in chemical mechanical polishing (CMP) of Cu metallization with ultra low-k materials as interlayer dielectrics. In this study we have investigated the polishing behavior of patterned Cu samples with underneath different low-k materials using two different slurries and a wide range of machine parameters. CMP micro tribometer was used to polish the samples with different rotations of platen (50 to 250 RPM) and down forces (1-6 PSI). Friction co-efficient and wear behavior were also investigated at different conditions. Optical and scanning electron microscopy was used to investigate the polished surface. It was observed that the two different Cu slurries used for polishing have marked effects on the polishing of Cu-low-k stack with respect to wear and delamination.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 767: Symposium F – Chemical-Mechanical Planarization , 2003 , F7.3
Copyright
Copyright © Materials Research Society 2003

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Jin, C. Lin, S. and Wetzel, J. T. J. Elec. Mater., 30, 284–289 (2001)Google Scholar
2. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA, 2002.Google Scholar
3. Merchant, S. Kang, S.H. Sanganeria, M. Schravendijk, B. van and Mountsier, T. JOM, June, 43-48 (2001).Google Scholar
4. Sikder, A. K. Irfan, I.M. Kumar, Ashok and Anthony, J.M. J. Elec. Mater., 30, 1527–31 (2001).Google Scholar
5. Mosig, K. Jacobs, T. Brennan, K. Rasco, M. Wolf, J. Augur, R. Microelectronic Engineering, 64, 11–24 (2002).Google Scholar
6. Malik, Farid and Hasan, Masood, Thin Solid Films, 270, 612–615 (1995).Google Scholar
7. Yu, C. Future Fab, 10, (2001).Google Scholar
8. Sikder, A. K. Giglio, Frank, Wood, John, Kumar, Ashok and Anthony, J.M. J. Elec. Mater., 30, 1522, (2001).Google Scholar
9. Sikder, A. K. and Kumar, Ashok, J. Elec. Mater, 10, 1016–1021 (2002).Google Scholar