Business/foundry driven requirements have necessitated the creation of modified ILD CMP processes for terminal metal-die planarization for BiCMOS SOC/MEMS applications. Therefore, despite much CMP process evolution, this paper ‘steps-back’ to test CMP assumptions first introduced within ILD process norms on these new applications at 10X typical process topographies. Evaluation of planarization targets, density effects, oxide budgets, as well as associated integration, throughput and metrology considerations within this expanded regime are discussed. ANOVA on inter- and intra-die (WIWNU and WIDNU) variation are used to quantify results throughout the work.