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Chemical Vapor Deposition and Electrode Technologies for (Ba,Sr)TiO3 Capacitor Used in Gigabit Dram

Published online by Cambridge University Press:  10 February 2011

K. Eguchi ,
K. Hieda ,
J. Nakahira ,
M. Kiyotoshi ,
M. Nakabayashi ,
S. Yamazaki ,
M. Izuha ,
T. Aoyama ,
K. Tsunoda  and
J. Lin
...Show all authors
K. Eguchi
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
K. Hieda
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
J. Nakahira
Affiliation:
Technology Development Division, Semiconductor Group, Fujitsu Limited, 1500, Mizono, Tado-Cho, Kuwana-Gun, Mie-ken 511–0192, Japan
M. Kiyotoshi
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
M. Nakabayashi
Affiliation:
Technology Development Division, Semiconductor Group, Fujitsu Limited, 1500, Mizono, Tado-Cho, Kuwana-Gun, Mie-ken 511–0192, Japan
S. Yamazaki
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
M. Izuha
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
T. Aoyama
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
K. Tsunoda
Affiliation:
Fujitsu Laboratories Limited, 10–1, Wakamiya, Morinosato, Atsugi 243–0197Japan
J. Lin
Affiliation:
Technology Development Division, Semiconductor Group, Fujitsu Limited, 1500, Mizono, Tado-Cho, Kuwana-Gun, Mie-ken 511–0192, Japan
K. Nakamura
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
S. Niwa
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
H. Tomita
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
A. Shimada
Affiliation:
Technology Development Division, Semiconductor Group, Fujitsu Limited, 1500, Mizono, Tado-Cho, Kuwana-Gun, Mie-ken 511–0192, Japan
Y. Kohyama
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
Y. Ishibashi
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
Y. Fukuzumi
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
T. Arikado
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
K. Okumura
Affiliation:
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Japan, [email protected]
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Abstract

We review our capacitor technology using (Ba,Sr)TiO3 (BST) as a capacitor dielectric for dynamic random access memory (DRAM) application. Among a number of issues for BST capacitor process integration in DRAM cells, two important technologies are discussed. As an electrode technology, we propose All PErovskite Capacitor (APEC) technology, in which conducting perovskite oxide of SrRuO3 (SRO) is used as capacitor electrodes. For chemical vapor deposition (CVD) of BST, we propose In-situ Multi-Step (IMS) process, which is a sequential repetition of low temperature deposition of ultra thin BST film and crystallization in the same chamber. By using APEC technology and IMS CVD process of BST, we can simultaneously achieve good electrical characteristics (low leakage current and high permittivity) and good step coverage. The combination of APEC technology and IMS CVD process of BST is a promising BST capacitor process technology for future DRAMs.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 596: Symposium Y – Ferroelectric Thin Films VIII , 1999 , 3
Copyright
Copyright © Materials Research Society 2000

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