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Characterization of Electromigration Failures Using a Novel Test Structure

Published online by Cambridge University Press:  15 February 2011

Martin Gall
Affiliation:
Advanced Products Research and Development Laboratory, Motorola, 3501 Ed Bluestein Blvd., Austin, TX 78721
Dharmesh Jawarani
Affiliation:
Advanced Products Research and Development Laboratory, Motorola, 3501 Ed Bluestein Blvd., Austin, TX 78721
Hisao Kawasaki
Affiliation:
Advanced Products Research and Development Laboratory, Motorola, 3501 Ed Bluestein Blvd., Austin, TX 78721
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Abstract

Electromigration failures occur at locations where Al mass transport flux divergences exhibit a maximum. In VLSI circuits, these locations correspond to tungsten plug contact / via areas. Characterizing and understanding electromigration failures at tungsten plug contact / via areas are essential in assuring the reliability of 0.5 μm and smaller devices. In this study, a novel test structure with four vias connecting metal 1 and metal 2 levels was used to separate two stages in the Al-Cu interconnect electromigration process. These stages are the incubation time during which Cu in the Al-Cu alloy is swept away from the via area and an Al drift time which leads to interconnect failure. By the use of this structure, a non-destructive method has been established to measure incubation times and Al drift times separately, monitoring discrete increases in line resistance corresponding to a sequential depletion of all four vias. Activation energies for both processes have been determined. The temperature dependence of the incubation time is characterized by a thermal activation energy of Q=1.08 ± 0.15 eV, indicative of Cu grain boundary diffusion through Al grains. Al depletion was found to occur with an activation energy of Q=0.72 ± 0.12 eV. We therefore conclude that Al self-grain boundary diffusion constitutes the Al depletion mechanism. The application of this novel test structure enables distinct determination of dominating failure mechanisms under operating conditions and therefore provides a realistic reliability assessment of actual on-chip interconnect structures.

Type
Research Article
Copyright
Copyright © Materials Research Society 1996

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