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Can We Exploit Imprint in Ferroelectric Thin Film Capacitors for Memory Applications?

Published online by Cambridge University Press:  15 February 2011

In Kyeong Yoo  and
Seshu B. Desu
In Kyeong Yoo
Affiliation:
Samsung Advanced Institute of Technology, P.O. Box 111, Suwon 440–600, Korea
Seshu B. Desu
Affiliation:
Department of Materials Science Engineering, VA Tech, Blacksburg, VA 24061
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Abstract

Imprint was observed for fatigued PZT (Zr/Ti = 53/47) capacitors which were subjected to a thermal cycle (at 80°C for a period of time). It was also observed for capacitors whose top electrode was defined by ion milling. In addition, capacitors with an asymmetric multilayered structure showed severe imprint problems. Based on the above observations, imprinting was categorized as:

1) Intrinsic imprint which is caused by inherent conditions such as device structure, configuration, and material composition.

2) Extrinsic imprint which is generated by external sources such as electrical stress, thermal stress, time, and processing.

Imprint mechanisms were discussed for each imprinting category. Most importantly, based on partial switching, a new memory logic was suggested. It is shown that stable imprinting may be useful for low density FRAM applications when the proposed new memory logic is applied. Reliability of the new logic was also shown to be significantly better than conventional operation.

Keywords

ImprintDepolarizationPartial switchingBistable state.
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 361: Symposium I2 – Ferroelectric Thin Films IV , 1994 , 79
Copyright
Copyright © Materials Research Society 1995

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References

REFERENCES

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