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Benefits and Trade-offs in Multi-Level Air Gap Integration

Published online by Cambridge University Press:  01 February 2011

Romano Hoofman
Affiliation:
[email protected], Philips Research, CMOS Module Integration, Kapeldreef 75, Leuven, N/A, B3001, Belgium
Roel Daamen
Affiliation:
[email protected], Philips Research, Kapeldreef 75, Leuven, N/A, B3001, Belgium
Viet Nguyenhoang
Affiliation:
[email protected], Philips Research, Kapeldreef 75, Leuven, N/A, B3001, Belgium
Julien Michelon
Affiliation:
[email protected], Philips Research, Kapeldreef 75, Leuven, N/A, B3001, Belgium
Laurent G. Gosset
Affiliation:
[email protected], Philips Semiconductor, Crolles R&D, Crolles, N/A, N/A, France
Vincent Arnal
Affiliation:
[email protected], ST Microelectronics, Crolles R&D, Crolles, N/A, N/A, France
Jean de Pontcharra
Affiliation:
[email protected], CEA-LETI, Grenoble, N/A, N/A, France
Frederic Gaillard
Affiliation:
[email protected], CEA-LETI, Grenoble, N/A, N/A, France
Rudy Caluwaerts
Affiliation:
[email protected], IMEC, Leuven, N/A, N/A, Belgium
Christophe Bruynseraede
Affiliation:
[email protected], IMEC, Leuven, N/A, N/A, Belgium
Gerald Beyer
Affiliation:
[email protected], IMEC, Leuven, N/A, N/A, Belgium
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Abstract

In this paper, two different air gap integration approaches are discussed in detail. Firstly, air gaps can be created using sacrificial materials, which are selectively removed through a capping layer either by wet- or dry-etching or by thermal decomposition. The second class benefits from the non-conformal deposition of different CVD dielectrics, which creates air gaps for narrow spaced lines. The benefit of air gaps in terms of capacitance reduction in multilevel interconnects is well known, therefore the authors will mainly concentrate on the challenges associated with the introduction of air gaps in interconnect systems. It will be shown that interconnect containing air gaps does not suffer more from reliability challenges than interconnects with porous low-k dielectrics. Therefore, air gaps can be considered as a viable option for the 32nm node and beyond.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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References

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