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Arc Suppression and Defect Reduction in Semiconductor Metallization

Published online by Cambridge University Press:  10 February 2011

Xiangbing Li ,
David Loo ,
Brad Stimson ,
Scott Seamons  and
Murali Narasimhan
Xiangbing Li
Affiliation:
PVD Division, Applied Materials Inc., 2151 Mission College Blvd., Santa Clara, CA 95054
David Loo
Affiliation:
PVD Division, Applied Materials Inc., 2151 Mission College Blvd., Santa Clara, CA 95054
Brad Stimson
Affiliation:
PVD Division, Applied Materials Inc., 2151 Mission College Blvd., Santa Clara, CA 95054
Scott Seamons
Affiliation:
PVD Division, Applied Materials Inc., 2151 Mission College Blvd., Santa Clara, CA 95054
Murali Narasimhan
Affiliation:
PVD Division, Applied Materials Inc., 2151 Mission College Blvd., Santa Clara, CA 95054
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Abstract

Suppression of arcing between the target and plasma during PVD is a key issue for defect reduction, yield improvement and high quality metallization in microelectronics manufacturing. An integrated mini sparcle product has been designed for Endura HP PVD™ sputtering sources. Characteristics of arcing and mechanisms for suppression are discussed here. Process characterization with Ti, TiN and Al sputtering proves that the arc suppression unit has little adverse impact on film properties. The uniformity of reactive sputtered TiN is improved with arc suppression. Marathon evaluation indicates significant reduction in TiN defect and Interconnect metal stack defect. The study of the application for a wide variety of materials (Al, Ti, TiN, SiW, Si) establishes a correlation between deposition rate loss and sputtering power and this relation is found to be almost independent of the materials sputtered. The impact on throughput for typical metal stack is also presented in this paper.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 510: Symposium D – Defect & Impurity Engineered Semiconductors & Devices II , January 1998 , 259
Copyright
Copyright © Materials Research Society 1998

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References

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