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Applications of MeV Ion Implantation in Semiconductor Device Manufacturing

(Invited Paper)

Published online by Cambridge University Press:  21 February 2011

John O. Borland
John O. Borland*
Affiliation:
Genus, Ion Technology Division, 4 Muliken Way, Newburyport, MA, 01950.
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Abstract

Use of MeV ion implantation for mass production of CMOS devices at 0.5um design rule and beyond is now being accepted around the world for 16Mb DRAM, 16Mb Flash memory and CMOS logic/microprocessor technologies. Incorporating MeV well formation for twin well and triple well results in a reduction of up to 3 masking layers corresponding to process simplification and manufacturing cost reduction of 10% to 16%. For CMOS logic application, a new structure called BILLI (Buriedjmplanted Layer for Lateral Isolation) is showing great promise for latch-up free CMOS and when combined with hydrogen denuded bulk Czochraliski (CZ) grown silicon wafers, has the potential to replace epitaxial wafers with improved device performance. This paper will review MeV ion implantation use for these various CMOS applications.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 354: Symposium A – Beam Solid Interactions for Materials Synthesis and Characterization , 1994 , 123
Copyright
Copyright © Materials Research Society 1995

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