Aluminum (Al) gate fill has been implemented in Replacement Metal Gate (RMG) due to its low resistivity. Titanium (Ti) has been widely used as wetting layer for Al to fill the gates. For low resistance gate fill in structures with small feature size and high aspect ratio, Ti-Al metal fill becomes increasingly more challenging as we move from 20nm into 14nm FinFET and 3D type structures.

Cobalt (Co) is a good wetting film for Al with better fill performance and lower resistance than Ti-Al based process. However, due to the difference in corrosion potential between Al and Co, Chemical Mechanical Planarization (CMP) creates pitting type defects on Al-Co film that increases resistance variability across pattern density. CMP induced corrosion is separated in two parts; first is the static Co corrosion happened in the acidic chemical environment in the Al slurry. Second is the galvanic corrosion from Co-Al metal boundary due to high metal electrical potential. Static corrosion can be resolved by adding a Co corrosion inhibitor in the slurry formulation1. Galvanic corrosion can be minimized by controlling Co thickness deposition and formation of complete intermetallic phase. By controlling the removal rate with respect to corrosion rate we were able to suppress corrosion significantly.

We looked into compositions where the corrosion potential (Ecorr) gap between Al and Co is reduced to ≤10mV leading to reduced galvanic currents. Stabilization of the corrosion currents in both Al and Co was observed using potentiodynamic scans. The effect of pH, several oxidizers and additives on the open circuit potentials (Eoc) of Al and Co was investigated and it was found that solutions of KMnO4, saccharides and sulfonate group containing compounds help reduce the Ecorr gap in between Al and Co to ∼10 mV.

Controlling the Al gate height across pattern densities and gate lengths to within few nm is another challenge for Al CMP. The industry widely used approach is to clear all Al using a slurry with high selectivity to dielectric, followed by a CMP step using a non-selective Al-to-oxide slurry. Both polishing steps need to be optimized in parallel in order to remove the incoming spacer SiN divot, minimize Al loss on gates with high pattern density or long gate length, minimize oxide loss on large open areas while maintaining low defectivity.

In this paper we are presenting an innovate Al CMP process that demonstrated low gate resistance with tight distribution up to 80% pattern density. This work has been supported by the independent Bulk CMOS and SOI technology development projects at the IBM Microelectronics Division Semiconductor Research & Development Center, Hopewell Junction, NY 12533.