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Use of Porous Silicon to Minimize Oxidation Induced Stacking Fault Defects in Silicon

Published online by Cambridge University Press:  03 September 2012

S.-Y. Shieh  and
J. W. Evans
S.-Y. Shieh
Affiliation:
Materials Science Division, Lawrence Berkeley Laboratory and Department of Materials Science and Mineral Engineering, University of California, Berkeley, CA 94720
J. W. Evans
Affiliation:
Materials Science Division, Lawrence Berkeley Laboratory and Department of Materials Science and Mineral Engineering, University of California, Berkeley, CA 94720
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Abstract

Present methods for minimizing stacking fault defects, generated during oxidation of silicon, include damaging the back of the wafer or depositing poly-silicon on the back. In either case a highly defective structure is created and mis is capable of gettering either self-interstitials or impurities which promote nucleation of stacking fault defects.

A novel method of minimizing these defects is to form a patch of porous silicon on the back of the wafer by electrochemical etching. Annealing under inert gas prior to oxidation may then result in the necessary gettering. Experiments were carried out in which wafers were subjected to this treatment. Subsequent to oxidation, the wafers were etched to remove oxide and reveal defects. The regions of the wafer adjacent to the porous silicon patch were defect-free, whereas remote regions had defects. Deep level transient spectroscopy has been used to examine the gettering capability of porous silicon, and the paper discusses the mechanism by which the porous silicon getters.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 262: Symposium E – Defect Engineering in Semiconductor Growth, Processing and Device Technology , 1992 , 981
Copyright
Copyright © Materials Research Society 1992

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References

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