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Ultra Thin High Quality Ta2O5 Gate Dielectrics Prepared by In-situ Rapid Thermal Processing

Published online by Cambridge University Press:  10 February 2011

H. F. Luan ,
S. J. Lee ,
C. H. Lee ,
A. Y. Mao ,
R. Vrtis ,
D. Roberts  and
D. L. Kwong
H. F. Luan
Affiliation:
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712
S. J. Lee
Affiliation:
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712
C. H. Lee
Affiliation:
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712
A. Y. Mao
Affiliation:
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712
R. Vrtis
Affiliation:
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of TexasSchumacher, Calsbad, CA 92009
D. Roberts
Affiliation:
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of TexasSchumacher, Calsbad, CA 92009
D. L. Kwong
Affiliation:
Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712
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Abstract

In this paper, ultra thin CVD Ta2O5 stacked gate dielectrics (Teq∼14Å-22Å) was fabricated by in-situ RTP processing. The leakage current of Ta2O5 devices is 103× lower leakage current compared to SiO2 of identical thickness for devices with Teq between 18Å-22Å. While Teq<18Å, the leakage current follows same train and J∼10−3A/cm2 for Ta2O5 stacked gate dielectrics with Teq=14Å. Superior interface properties and reliability have been obtained.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 567: Symposium R – Ultrathin SiO2 and Higg-K Materials for ULSI Gate Dielectrics , 1999 , 385
Copyright
Copyright © Materials Research Society 1999

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References

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