The Metal-Ferroelectric-Metal-Oxide-Silicon (MFMOS) one transistor memory requires a metal electrode directly on top of the thin gate oxide. The gate oxide used in our present MFMOS one transistor memory processing is 30 Å SiO2. Ir has been chosen for the bottom electrode and TaN was used as the barrier layer between the Ir and thin gate oxide. It has been shown from previous studies that a TaN barrier layer can effectively prevent the formation of iridium silicide and can enhance the adhesion between Ir and Si or SiO2 substrates. But it is more important that the TaN itself is stable and will not react with the gate oxide during ferroelectric material deposition, annealing and subsequent processing. In this paper, TaN barriers with different deposition conditions have been deposited on 30 Å gate oxide. 1500 Å Ir was deposited on the TaN barrier layer. Capacitors of Ir/TaN/gate SiO2/Si were defined by dry etching. Series RTP annealing were performed in oxygen from 500 to 650 °C with annealing times from 5 min to 90 min. The capacitor was also annealed in a nitrogen ambient at 1000°C for 10s. C-V and I-V studies were used to characterize the stability of the Ir/TaN/Gate SiO2 structure. It was observed that the Ir/TaN/Gate SiO2 is very stable during the above mentioned annealing conditions. The consumption and further oxidation of the gate oxide is negligible and would depend on the deposition condition of the TaN barrier layer. With optimized deposition conditions, a 220 Å TaN barrier layer can effectively prevent any iridium silicide formation and will not degrade the gate oxide during annealing processing. The interfaces between the TaN and gate SiO2 and between the gate SiO2 and Si substrate can be further improved by forming gas annealing.