The effects of high gate voltage Vg stress on the stability of non-hydrogenated and hydrogenated short p-channel polysilicon thin-film transistors (TFTs) are investigated for operation in the saturation region. The degradation mechanisms were identified from the evolution with stress time of the static device parameters. In non-hydrogenated TFTs, transconductance overshoot and a turnover behavior in the threshold voltage were observed. The results indicate that hot-electron trapping near the drain dominates in the initial stages of stress and channel holes are injected into the gate oxide followed by interface states generation as the stress proceeds further. In hydrogenated TFTs, first an effective shortening of the channel length is observed due to trapping of hot-electrons. As the stress proceeds further, donor-type interface states are generated and the electric field near the drain increases due to built-up of positive charge resulted from trapping of hot-holes in these states.