Hostname: page-component-78c5997874-4rdpn Total loading time: 0 Render date: 2024-11-19T22:56:17.202Z Has data issue: false hasContentIssue false
  • English
  • Français

Source/Drain Overlap Length Dependence of VT in Thin Film Transistor on a-IGZO Channel Deposited by RF and DC Sputtering

Published online by Cambridge University Press:  01 February 2011

Dong Ho Nam ,
Kwang-Il Choi ,
Sung Soo Park ,
Jae Kyeong Jeong  and
Ga Won Lee
Dong Ho Nam
Affiliation:
[email protected], Chungnam National University, Daejeon, Korea, Republic of
Kwang-Il Choi
Affiliation:
[email protected], Chungnam national university, Daejeon, Korea, Democratic People's Republic of
Sung Soo Park
Affiliation:
[email protected], Chungnam National University, Daejeon, Korea, Republic of
Jae Kyeong Jeong
Affiliation:
[email protected], Samsung SDI Co., Ltd, Yongin, Korea, Republic of
Ga Won Lee
Affiliation:
[email protected], Chungnam National University, Daejeon, Korea, Republic of
Get access

Abstract

The ZnO TFTs have attracted much attention as key component for flexible displays because they can be fabricated on plastic substrates at low temperature and exhibit good electrical performance. However, the ZnO films are polycrystalline with grain boundaries even if formed at room temperature, which deteriorate the uniformity of TFT characteristics. A few research groups have reported high performance amorphous indium-gallium-zinc oxide TFTs to solve the native problem of nonuniformity of ZnO TFTs. However, there are few researches on the process parameter effects on the variation of a-IGZO TFT characteristics. In this study, we focus on the effect of the source/drain overlap length on threshold voltage(VT) of a-IZO TFTs with differentiating channel deposition method. The experimental structures for this work are bottom-gated TFTs with a-IGZO channel that were deposited by RF and DC magnetron sputtering on glass. RF and DC sputtering were carried out by magnetron power density of (1.4 W/cm2)/ (2.0 W/cm2) in Ar/O2 gas ratio of (65/35)/(72/28), and the entire gas pressure were 5.0 mTorr and 3.4 mTorr. The width/length(um/um) of device was split to 10/7,10/10,10/30,10/50. Each of the patterns has seven source/drain overlap length: -3um,-2um,-1um,0um,1um,2um,3um. We extracted VT of RF and DC through the VG-ID curve. There are significant VT difference in both RF and DC according to the overlap length: VT of DC(RF) is 1.31(0.74)V at W/L=10/50 and 10.21(5.74)V at W/L=10/30. VT increases definitely where less than 1um overlap length and short channel TFT is more influenced by overlap length, which is more severe in RF group. We calculated total channel resistance (RT) from VD-ID curve. RT of devices with the positive overlap can be expressed by RT, Postive=Rch+Rc. Here, Rch is net channel resistance which becomes smaller when channel length decreases and Rc is contact resistance. RT with negative overlap, is RT, Negative=Rch+Rc+Roffset. Roffset is offset resistance formed by negative overlap and can be extracted by subtracting RT, Postive from total RT, Negative. The RT of DC(RF) at offset channel length of-1um,-2um,and-3um is 4.43105(2.7 106)cm, 1.17 106(3.48 106)cm, and 1.46 106(4.73 106)cm, respectively(W/L=10/10um) RF group which shows inferior electrical characteristics such as lower mobility and larger subthreshold slope to DC, have larger Roffset than the DC. This implies that the devices require a bit of positive source/drain overlap length for uniform VT especially when the channel resistance is high. But Overlap region causes difficulties in the device area to be miniaturized. In summary, as the source/drain overlap length decreases to negative value, the threshold voltage of a-IGZO TFTs increases sharply and these tendency strongly depends on a-IZO film quality, which means the overlap length is very important control parameter of a-IGZO TFTs for the uniform threshold voltage especially when the channel resistance is high

Keywords

Znthin filmamorphous
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1108: Symposium A – Performance and Reliability of Semiconductor Devices , 2008 , 1108-A09-13
Copyright
Copyright © Materials Research Society 2009

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Fortunato, Elvira M. C., Barquinha, Pedro M. C., et al., “Wide-bandgap high-mobility ZnO thin-film transistors produced at room temperature,” Appl. Phys. Lett. 85, 13 (2004)Google Scholar
2. Nomura, K., Ohta, H., Takagi, A., Kamiya, T., Hirano, M., and Hosono, H., “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, pp. 488–492, Nov. (2004)Google Scholar
3. Kim, Young-Jin a,), Kim, Hyeong-Joon “Trapped oxygen in the grain boundaries of ZnO polycrystalline thin films prepared by plasma-enhanced chemical vapor deposition,” Materials Letters, pp. 159–163 Google Scholar
4. Park, Jin-Seong, Jeong, Jae Kyeong, a_ Mo, Yeon-Gon, and Kim, Hye Dong, “Improvements in the device characteristics of amorphous indium gallium zinc oxide thin-film transistors by Ar plasma treatment,” Appl. Phys. Lett. 90, 262106 (2007)Google Scholar
5. Hisato, , Sano, Maeaufmi, “High-mobility thin-film transistor with amorphous InGaZnO4 fabricated by room temperature rf-magnetron sputteringch” Appl. Phys.Lett. 89, 112123 (2006).Google Scholar
6. Jeong, Jong Han, Yang, Hui Won, “Origin of Subthreshold Swing Improvement in Amorphous Indium Gallium Zinc Oxide Transistors” Electrochem. Solid State Lett., vol. 11, no.6, pp. H157–H159, 2008.Google Scholar
7. Tanaka, K., Arai, H., and Kohda, S., “Characteristics of offset-structure polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., vol. 9, no. 1, 1988.Google Scholar
8. Park, Cheol-Min, Min, Byung-Hyuk, Jun, Jae-Hong, Yoo, Juhn-Suk, and Han, Min-Koo “Self-Aligned Offset Gated Poly-Si TFT's with a Floating Sub-Gate” IEEE Electron Device Lett, vol. 18, no. 1, 1997.Google Scholar
9. Zhu, Chunxiang, Sin, Johnny K. O. “A Novel Self-Aligned Offset-Gated Polysilicon TFT Using High-k Dielectric Spacers” IEEE Electron Device Lett, vol.5, no. 4, 2004.Google Scholar