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Simulation and Design of a Silicon Nanowire based Phase Change Memory Cell

Published online by Cambridge University Press:  13 June 2012

Ramin Banan Sadeghian ,
Yusuf Leblebici  and
Ali Shakouri
Ramin Banan Sadeghian
Affiliation:
Baskin School of Engineering, University of California at Santa Cruz, 1156 High Street, Santa Cruz, CA 95064, U.S.A.
Yusuf Leblebici
Affiliation:
Microelectronic Systems Laboratory, Swiss Federal Institute of Technology (EPFL), ELD 340, Station 11,CH-1015 Lausanne, Switzerland.
Ali Shakouri
Affiliation:
Baskin School of Engineering, University of California at Santa Cruz, 1156 High Street, Santa Cruz, CA 95064, U.S.A. School of Electrical and Computer Engineering, Purdue University, 465 Northwestern Ave., West Lafayette, IN 47907, U.S.A.
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Abstract

In this work we present preliminary calculations and simulations to demonstrate feasibility of programming a nanoscale Phase Change Random Access Memory (PCRAM) cell by means of a silicon nanowire ballistic transistor (SNWBT). Memory cells based on ballistic transistors bear the advantage of having a small size and high-speed operation with low power requirements. A one-dimensional MOSFET model (FETToy) was used to estimate the output current of the nanowire as a function of its diameter. The gate oxide thickness was 1.5 nm, and the Fermi level at source was set to -0.32 eV. For the case of VDS = VGS = 1 V, when the nanowire diameter was increased from 1 to 60 nm, the output power density dropped from 109 to 106 W cm-2 , while the current increased from 20 to 90 μA. Finite element electro-thermal analysis were carried out on a segmented cylindrical phase-change memory cell made of Ge2Sb2Te5 (GST) chalcogenide, connected in series to the SNWBT. The diameter of the combined device, d, and the aspect ratio of the GST region were selected so as to achieve optimum heating of the GST. With the assumption that the bulk thermal conductivity of GST does not change significantly at the nanoscale, it was shown that for d = 24 nm, a ‘reset’ programming current of ID = 80 μA can heat the GST up to its melting point. The results presented herein can help in the design of low cost, high speed, and radiation tolerant nanoscale PCRAM devices.

Keywords

electronic materialmemorynanoscale
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1431: Symposium F – Phase-Change Materials for Memory and Reconfigurable Electronics Applications , 2012 , mrss12-1431-f11-03
Copyright
Copyright © Materials Research Society 2012

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References

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