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Shallow Junctions for Sub-100 Nm Cmos Technology
Published online by Cambridge University Press: 21 March 2011
Abstract
This paper studies the use of ion implantation and rapid thermal annealing for the fabrication of shallow junctions in sub-100 nm CMOS technology. Spike annealing recipes were optimized on the basis of delta-doping diffusion experiments and shallow junction characteristics. In addition, using GeF2 pre-amorphization implants in combination with low-energy BF2 and spike annealing, p-type junctions depths of 30 nm were obtained with sheet resistances as low as 390 Ω/sq. The combined finetuning of implantation and annealing conditions is expected to enable junction scaling into the 70-nm CMOS technology node.
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- Copyright © Materials Research Society 2001
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