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Sequential Process Modeling for Determining Process-Induced Thermal Stress in Advanced Cu/Low-k Interconnects
Published online by Cambridge University Press: 01 February 2011
Abstract
The thermomechanical reliability of Cu/low-k interconnects, which is directly related to yield problems and premature device failures, has been a major issue. The development of a manufacturing process, which can satisfy the most stringent reliability standards, requires detailed information on the thermomechanical behavior of Cu/low-k interconnects. The thermomechanical behavior of Cu/low-k interconnects is complicated by the fact that processinduced thermal stresses are developed during the manufacturing process. A conventional finite element analysis (FEA) approach has some difficulties to model Cu/low-k interconnects that keep changing during process steps. Therefore, a sequential process modeling technique has been developed to simulate the interconnect behavior to substantially any level of detail and understand the complex thermomechanical behavior of Cu/low-k interconnects while being manufactured. In this paper, we briefly describe a sequential process modeling technique and demonstrate how we use the modeling technique to solve a Cu/SiC delamination problem in a Cu/SiLK* semiconductor dielectric dual damascene test structure.
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- Copyright © Materials Research Society 2003
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