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Self-Aligned Nanocrystalline Silicon Thin-Film Transistor With Deposited n+ Source/Drain Layer

Published online by Cambridge University Press:  01 February 2011

I-Chun Cheng  and
Sigurd Wagner
I-Chun Cheng
Affiliation:
[email protected], National Taiwan University, Graduate Institute of Electro-Optical Engineering, National Taiwan University, Min-Da Hall, R621,, No.1, Sec.4, Roosevelt Road, Taipei, 10617, Taiwan, +886-2-3366-9648, +886-2-2367-7467
Sigurd Wagner
Affiliation:
[email protected], Princeton University, Department of Electrical Engineering and PRISM, Princeton, NJ, 08544, United States
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Abstract

We demonstrated self-aligned nanocrystalline silicon (nc-Si:H) n-channel thin film transistors (TFTs) with directly deposited n+ layer. The silicon layers were deposited by plasma-enhanced chemical vapor deposition at a substrate temperature of 150°C. The TFTs were made in a staggered top-gate, bottom-source/drain geometry with a seed layer underneath. The self-alignment of top-gate to the bottom-source/drain was achieved by backside exposure photolithography through the glass substrate and the silicon layers, followed by a lift-off process. An extent of gate to source/drain overlap of 1.5 mm was obtained. The self-aligned TFTs have similar characteristics to their non-self-aligned counterpart. This result represents an important step toward directly deposited nc-Si:H TFT backplanes on plastic substrates.

Keywords

Sichemical vapor deposition (CVD) (deposition)electronic material
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 989: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology-2007 , 2007 , 0989-A11-02
Copyright
Copyright © Materials Research Society 2007

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