Layered samples of cadmium telluride grown epitaxially on gallium arsenide substrates have been investigated by means of scanning tunneling microscopy (STM). The surface geometric and electronic structures are both of interest. Techniques were developed to remove the native oxide by etching, or to create a fresh surface by cleaving, and to protect them from oxidation by employing mineral or paraffin oil media. STM studies were conducted within the protective medium. These techniques were adapted and tested for both etched and cleaved samples of Si, CdTe and HgTe. The currentvoltage characteristics of the CdTe surface were investigated during dynamic changes of the tunnel current and barrier height while the probe-to-sample separation (gap) was static. Recorded values are shown for current versus bias for several constant gap values. A range of bias values has been employed to test a possible solution for the problem of interference between the contributions from geometric and electronic structure factors.