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Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing

Published online by Cambridge University Press:  28 July 2011

Takeo Matsuki ,
Yasushi Akasaka ,
Kiyoshi Hayashi ,
Masataka Noguchi ,
Koji Yamashita ,
Hideyuki Syoji ,
Kazuyoshi Torii ,
Naoki Kasai  and
Tsunetoshi Arikado
Takeo Matsuki
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Yasushi Akasaka
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Kiyoshi Hayashi
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Masataka Noguchi
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Koji Yamashita
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Hideyuki Syoji
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Kazuyoshi Torii
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Naoki Kasai
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
Tsunetoshi Arikado
Affiliation:
Research Department 1, Semiconductor Leading Edge Technologies, Inc. 16-1 Onogawa, Tsukuba-shi, Ibaraki-ken, 305-8569, Japan
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Abstract

A Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 811: Symposia D/E – Integration of Advanced Micro-and Nanelectronic Devices-Critical Issues and Solutions , 2004 , D3.13
Copyright
Copyright © Materials Research Society 2004

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References

REFERENCES

[1] Tsai, W., Ragnarsson, L. A., Pantisano, L., Chen, P.J., Onsia, B., Schram, T., Cartier, E., Kerber, A., Young, E., Caymax, M., Gendt, S. De and Heyns, M., Tech. Dig. IEDM 2003, p.311, (2003)Google Scholar
[2] Ohji, H., Mutoh, A., Torii, K., Mitsuhashi, R., Horiuchi, A., Maeda, T., Itoh, H., Kawahara, T., Hayashi, K., Sasaki, T., Kasai, N., Kitajima, H., Yasuhira, M. and Arikado, T., Ext. Abst. SSDM, p.166 (2003)Google Scholar
[3] Chatterjee, A., Chapman, R.A., Joyner, K., Otobe, M., Hattangady, S., Bevan, M., Brown, G.A., Yang, H., He, Q., Rogers, D., Fang, S.J., Kraft, R., Rotondaro, A.L.P., Terry, m., Brennan, K., Aur, S.-W., Hu, J.C., Tsai, H-L, Jones, P., Wilk, G., Aoki, M., Rodder, M. and Chen, I.-C., Tech. Dig. IEDM, p.777 (1998)Google Scholar
[4] Yagishita, A., Saito, T., Nakajima, K., Inumiya, S., Akasaka, Y., Ozawa, Y., Minamihara, G., Yano, H., Hieda, K., Suguro, K., Arikado, T. and Okumura, K., Tech. Dig. IEDM, p.785 (1998)Google Scholar
[5] Yamashita, K., Nishimori, H., Yoshioka, M., Kusuda, T., Arikado, T. and Okumura, K., Proc. International symposium on Semiconductor Manufacturing, p.153 (2003)Google Scholar
[6] Nishinohara, K., Ito, T. and Suguro, K., Proc. International symposium on Semiconductor Manufacturing, p.175 (2003)Google Scholar
[7] Matsuki, T., Torii, K., Maeda, T., Syoji, H., Kiyono, K., Akasaka, Y., Hayashi, K., Kasai, N. and Arikado, T., Proc. The 2004 International Conference on Microelectronic Test Structures, p.105 (2004)Google Scholar
[8] Ootsuka, F., IEEE Trans. Electron Devices, Vol.49, No.12, p.2345 (2002)Google Scholar
[9] Mitsuhashi, R., Horiuchi, A., Uedono, A. and Torii, K., Ext. Abst. International Workshop on Gate Insulator, p.150 (2003)Google Scholar
[10] Kim, W.S., Kawahara, T., Itoh, H., Horiuchi, A., Muto, A., Maeda, T., Mitsuhashi, R., Torii, K. and Kitajima, H., Ext. Abst. SSDM, p.806 (2003)Google Scholar