The metal gate high k interaction is one of the dominant processes influencing the electrical performance (Vt, charge accumulation,..) of advanced gate stacks. These interactions are influenced by the entire thermal budget and the presence of reactive elements (on top/ within the material gate) such that relevant measurements can only be performed after a full processing cycle and on a complete gate stack.

In such cases the relevant metal gate high k interface is a buried interface located below the metal gate (+ Si cap) and is not accessible for standard characterization methods like x-ray photoemission spectroscopy (XPS) due the limited escape depth of the photoelectrons. Moreover the presence of a conductive metal gate prevents the application of techniques such as conductive atomic force microscopy (C-AFM), to probe the local distribution of the defects, trapping sites and local degradation upon stressing. XPS in combination with layer removal steps like ion beam sputtering will destroy the bonding information and is thus not applicable. Chemical etching of the metal gate stack prior to the XPS measurements requires an extremely precious control of the etching in order to stop 1-2 nm before the high k metal interface.

As an alternative we have developed a backside removal approach, that allows us to investigate using techniques such as XPS and C-AFM, the metal gate high k interface.