Hostname: page-component-586b7cd67f-gb8f7 Total loading time: 0 Render date: 2024-11-25T16:44:47.553Z Has data issue: false hasContentIssue false
  • English
  • Français

Pioneering Application of Corona Charge-Kelvin Probe Metrology to Noncontact Characterization of In0.53 Ga0.47 As/Al2O3/HfO2 Stack

Published online by Cambridge University Press:  24 July 2014

Alexandre Savtchouk ,
John D’Amico ,
Marshall Wilson ,
Jacek Lagowski ,
Wei-E Wang ,
Taewoo Kim ,
Gennadi Bersuker ,
Dmitry Veksler  and
Donghyi Koh
Alexandre Savtchouk
Affiliation:
Semilab SDI, LLC, 10770 N. 46th St., Suite E700, Tampa, FL 33617, U.S.A.
John D’Amico
Affiliation:
Semilab SDI, LLC, 10770 N. 46th St., Suite E700, Tampa, FL 33617, U.S.A.
Marshall Wilson
Affiliation:
Semilab SDI, LLC, 10770 N. 46th St., Suite E700, Tampa, FL 33617, U.S.A.
Jacek Lagowski
Affiliation:
Semilab SDI, LLC, 10770 N. 46th St., Suite E700, Tampa, FL 33617, U.S.A.
Wei-E Wang
Affiliation:
SEMATECH, 257 Fuller Rd #2200, Albany, NY 12203, U.S.A.
Taewoo Kim
Affiliation:
SEMATECH, 257 Fuller Rd #2200, Albany, NY 12203, U.S.A.
Gennadi Bersuker
Affiliation:
SEMATECH, 257 Fuller Rd #2200, Albany, NY 12203, U.S.A.
Dmitry Veksler
Affiliation:
SEMATECH, 257 Fuller Rd #2200, Albany, NY 12203, U.S.A.
Donghyi Koh
Affiliation:
SEMATECH, 257 Fuller Rd #2200, Albany, NY 12203, U.S.A.
Get access

Abstract

We report the first successful application of corona charging noncontact C-V and I-V metrology to interface and dielectric characterization of high-k/III-V structures. The metrology, which has been commonly used in Si IC manufacturing, uses incremental corona charge dosing, ΔQC, on the dielectric surface, and the measurement of surface voltage response, ΔVS, using a Kelvin-probe. Its application to In0.53Ga0.47As with a high-k stack required modifications related to the effects of dielectric trap induced voltage transients. The developed Corona Charge-Kelvin Probe Metrology adopted strictly differential measurements using ΔQC and ΔV, and corresponding differential capacitance rather than measurements based on total global charge, Q, and voltage, V, values.

Electrical characterization data including interface trap density, electrical oxide thickness, and dielectric leakage are presented for a sample containing an In0.53 Ga0.47 As channel overlaid with a bilayer (2nm Al2O3/5nm HfO2) dielectric stack that is considered to be very promising for application in performance NFETs with high-mobility channels.

Keywords

III-Vdielectric propertiesdefects
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1691: Symposium BB – Materials for End-of-Roadmap Devices in Logic, Power and Memory , 2014 , mrss14-1691-bb05-02
Copyright
Copyright © Materials Research Society 2014 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

International Technology Roadmap for Semiconductors; “Front End Processes: ITRS 2012 Winter Public Conference”, Taiwan (2012).Google Scholar
del Alamo, J. A., Antoniadis, D., Gui, A., Kim, D. H., Kim, T. W., Lin, J., Lu, W., Vardi, A., and Zhao, X., 2013 IEEE International Devices Meeting, Washington, DC, 2.1.1-2.1.4 (2013).Google Scholar
Huang, J., Goel, N., Zhao, H., Kang, C. Y., Min, K. S., Bersuker, G., Oktyabrsky, S., Gaspe, C. K., Santos, M. B., Majhi, P., Kirsch, P.D., Tseng, H. H., Lee, J. C., Jammy, R., 2009 IEEE International Electron Devices Meeting (IEDM), 7–9 Dec. (2009).Google Scholar
Peide, D. Ye., J. of Vac. Sc. & Tech. A, 26(4), 697–704 (2008).Google Scholar
Oktyabrsky, S., and Ye, Peide D., eds. Fundamentals of III-V Semiconductor MOSFETs. Springer, 2010.CrossRefGoogle Scholar
Chau, R., Datta, S., and Majumdar, A., In Compound Semiconductor Integrated Circuit Symposium, CSIC'05. IEEE, 4, (2005).Google Scholar
Deora, S.. Bersuker, G., Loh, W. Y., Veksler, D., Matthews, K., Kim, T. W., Lee, R. T. P., Hill, R. J. W., Kim, D. H., Wang, W. E., Hobbs, C., and Kirsch, P. D., Trans. Dev. Mat. Reliability, 14, 300 (2014).CrossRefGoogle Scholar
Veksler, D., Nagaiah, P., Chidambaram, T., Cammarere, R., Tokranov, V., Yakimov, M., Chen, Y.-T., Huang, J., Goel, N., Oh, J., Bersuker, G., Hobbs, C., Kirsch, P. D. and Oktyabrsky, S., J. of Applied Physics, 112(5), 054504–054504 (2012).CrossRefGoogle Scholar
Sereni, G., Morassi, L., Vandelli, L., Larcher, L., Veksler, D. and Bersuker, G., “A new method for extracting interface state and border trap densities in high-k/III-V MOSFETs” IEEE Int. Reliab. Phys. Symp. (IRPS), 2014, (in press).Google Scholar
Veksler, D., Bersuker, G., Madan, H., Morassi, L., Verzellesi, G., Wang, Wei-E, Kirsch, P.D. “Extraction of interface state density in oxide/III-V gate stacks”, (2014), (unpublished).Google Scholar
Edelman, P., Hoff, A.M., Jastrzebski, L., Lagowski, J., SPIE, 2337, 154–164 (1994)Google Scholar
Wilson, M., Lagowski, J., Savtchouk, A., Jastrzebski, L., and D’Amico, J., in Gate Dielectric Integrity: Material, Process, and Tool Qualification, Gupta, D.C. and Brown, G.A., Editors, ASTM STP1382, pp. 74–90, American Society for Testing and Materials, West Conshohocken, PA (1999).Google Scholar
Sze, S. M., Physics of Semiconductor Devices, 2nd ed., pp. 362–369, John Wiley and Sons, Inc., New York, New York (1981).Google Scholar
Wilson, M., Marinskiy, D., Byelyayev, A., D’Amico, J., Findlay, A., Jastrzebski, L., and Lagowski, J., ECS Transactions, 3(3), 3–24 (2006).CrossRefGoogle Scholar
Veksler, D., Bersuker, G., Morassi, L., Yum, J. H., Verzellesi, G., Wang, W. E., and Kirsch, P. D., “Extraction of interfacial state density in high-k/III-V gate stacks: problems and solutions”. IEEE Nanotechnology Materials and Devices Conference, Oct. 7-9, 2013, National Cheng Kung University, Tainan, Taiwan.Google Scholar
Yuan, Y., Yu, B., Ahn, J., McIntyre, P. C., Asbeck, P. M., Rodwell, M. J. W., and Taur, Y., IEEE Trans. on El. Dev, 59(8), 2100–2106 (2012).CrossRefGoogle Scholar