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Nanocrystalline Silicon TFTs With 50 nm Thick Deposited Channel Layer, 10 cm2/Vs Electron Mobility and 108 On/Off Current Ratio

Published online by Cambridge University Press:  17 March 2011

Robert B. Min  and
Sigurd Wagner
Robert B. Min
Affiliation:
Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA
Sigurd Wagner
Affiliation:
Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA
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Abstract

Thin film transistors were made using 50 nm thick directly deposited nanocrystalline silicon channel layers. The transistors have coplanar top gate structure. The nanocrystalline silicon was deposited from discharges in silane, hydrogen and silicon tetrafluoride. The transistors combine a high electron field effect mobility of ∼ 10 cm2/Vs with a low “off” current of ∼ 10−14 A per µm of channel length, and an “on”/“off” current ratio of ∼ 108. This result shows that directly deposited silicon can combine high mobility with low “off” currents.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 664: Symposium A – Amorphous and Heterogeneous Silicon-Based Films-2001 , 2001 , A17.5
Copyright
Copyright © Materials Research Society 2001

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References

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