Hostname: page-component-78c5997874-fbnjt Total loading time: 0 Render date: 2024-11-18T12:19:26.927Z Has data issue: false hasContentIssue false
  • English
  • Français

Monolithic 3D Integration of Single-Grain Si TFTs

Published online by Cambridge University Press:  01 February 2011

Mohammad Reza Tajari Mofrad ,
Ryoichi Ishihara ,
Jaber Derakhshandeh ,
Alessandro Baiano ,
Johan van der Cingel  and
Cees Beenakker
Mohammad Reza Tajari Mofrad
Affiliation:
[email protected], ., ., ., ., ., Netherlands
Ryoichi Ishihara
Affiliation:
[email protected], Technical University of Delft, Department of Electrical Engineering, DIMES/ECTM, Delft, N/A, Netherlands
Jaber Derakhshandeh
Affiliation:
[email protected], Technical University of Delft, Department of Electrical Engineering, DIMES/ECTM, Delft, N/A, Netherlands
Alessandro Baiano
Affiliation:
[email protected], Technical University of Delft, Department of Electrical Engineering, DIMES/ECTM, Delft, N/A, Netherlands
Johan van der Cingel
Affiliation:
[email protected], Technical University of Delft, Department of Electrical Engineering, DIMES/ECTM, Delft, N/A, Netherlands
Cees Beenakker
Affiliation:
[email protected], Technical University of Delft, Department of Electrical Engineering, DIMES/ECTM, Delft, N/A, Netherlands
Get access

Abstract

Vertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. NMOS mobilities are 565 and 393 cm2/Vs and pMOS mobilities are 159 and 141 cm2/Vs, for the top and bottom layers respectively. A three-dimensional (3D) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer. The inverters showed an output voltage swing of 0 to 5 V with a switching voltage of around 2 V.

Keywords

thin filmlaser annealingcrystal growth
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1066: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology—2008 , 2008 , 1066-A20-06
Copyright
Copyright © Materials Research Society 2008

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1.- Saraswat, K.C. Mohammadi, F., “Effect of scaling of interconnections on the time delay of VLSI circuits”, IEEE Transactions on Electron Devices 29 (1982)Google Scholar
2.- Chen, V. W. C. , P. C. H. C. and Chan, M. “Three Dimensional CMOS Integrated Circuits on Large Grain Polysilicon Films”, International Electron Devices Meeting Technical Digest, 161-164 (2000)Google Scholar
3.- Matsumoto, T. Satoh, M. Sakuma, K. Kurino, H. Miyakawa, N. Itani, H. and Koyanagi, M. “New three-dimensional wafer bonding technology using the adhesive injection method”, Japanese Journal of Applied Physics Part 1-Regular Papers 37 (1998)Google Scholar
4.- Geis, M. W. Flanders, D. C. and Smith, H. I. “Crystallographic orientation of silicon on an amorphous substrate using an artificial surface-relief grating and laser crystallization”, Applied Physics Letters 35, 71 (1979)Google Scholar
5.- Reif, R. and Knott, J. E. J. E., , “Low-temperature process to increase the grain size in polysilicon films”, Electronics Letters 17, 586 (1981)Google Scholar
6.- Nishimura, T., Inoue, Y., Sugahara, K., Kusunoki, S., Kumamoto, T., Nakagawa, S., Nakaya, M., Horiba, Y., and Akasaka, Y., “Three dimensional IC for high performance image signal processor”, International Electron Devices Meeting 33, 111–114 (1987)Google Scholar
7.- Son, Yong-Hoon et al. , “Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity”, IEEE Symposium on VLSI Technology, 80-81 (2007)Google Scholar
8.- Paul, C. van der Wilt, B. D. Dijk, van, Bertens, G. J. Ishihara, R. and C. Beenakker, I. M. “Formation of location-controlled crystalline islands using substrate-embedded seeds in excimer-laser crystallization of silicon films”, Applied Physics Letters 79, 1819 (2001)Google Scholar
9.- Rana, Vikas et al. , “High Performance P-Channel Single-Crystalline Si TFTs Fabricated Inside a Location-Controlled Grain by u-Czochralski Process”, IEICE Transactions on Electronics, E87-C (11), 1943–1947 (2004)Google Scholar