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Low Resistivity CoSi2 Surface Layers for Use as Contacts in CMOS Processes

Published online by Cambridge University Press:  28 February 2011

Sarah A. Audet ,
Conor S. Rafferty ,
Alice E. White ,
Ken T. Short  and
Yong-Fen Hsieh
Sarah A. Audet
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Conor S. Rafferty
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Alice E. White
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Ken T. Short
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
Yong-Fen Hsieh
Affiliation:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, N.J. 07974
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Abstract

Uniform CoSi2 surface layers 30nm thick have been realized through room temperature implantation of Co+ through a resist or an oxide mask and low temperature (600°C) annealing. TEM studies show that the surface layers are polycrystalline with large, uniformly thick grains. Resistivity values as low as 181µΩ-cm have been obtained. Surface layers of TiSi2 have also been synthesized using a similar process. The ease of formation, the low resistivity and the smooth interfaces of the CoSi2 and TiSi2 surface layers make this technique a promising candidate for contacting source and drain junctions in sub-half-micron CMOS processes.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 224: Symposium F – Rapid Thermal and Integrated Processing I , 1991 , 109
Copyright
Copyright © Materials Research Society 1991

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