The impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.

The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.