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Interconnection Challenges of the 1990's

Published online by Cambridge University Press:  15 February 2011

Michael A. Fury
Michael A. Fury*
Affiliation:
IBM Corporation Zip 49X, Route 52, Hopewell Junction, NY 12533-6531, (914)894-3248, (914)892-6399, [email protected]
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Abstract

Silicon device performance has improved dramatically over the past two decades. During that time, the portion of total circuit delay attributable to interconnect wiring has increased to nearly half. Changes in the use of aluminum wiring and silicon oxide insulators must be considered to further improve performance.

The generation of ULSI circuitry now under development in the industry depends heavily on innovations in materials and processes to achieve significant improvements in wiring density and circuit performance. The subsequent generation places even greater demands on materials improvements for lower resistivity wiring and a lower dielectric constant insulator. Integrating materials and methods compatible with semiconductor processing while ensuring device reliability will create a significant financial challenge in addition to the technical challenge.

This presentation enumerates the interconnection challenges facing the materials scientist and the circuit designer. The ultimate limits in materials improvements are predictable and finite. Further improvements will be derived from design innovations such as treating interconnects as active rather than passive devices. Accurate physical modelling of MLM structures will complement even more complex electrical modelling. Manufacturing sciences will grow in sophistication if implementation is to succeed. The financial burden of these technical challenges will foster collaborations among semiconductor manufacturers, equipment vendors, and research universities.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 265: Symposium H – Materials Reliability in Microelectronics II , 1992 , 145
Copyright
Copyright © Materials Research Society 1992

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