Published online by Cambridge University Press: 16 February 2011
In the microelectronics industry titanium disilicide (TiSi2) is used as a material for metallization and interconnection on silicon based integrated circuits. In the C54 structure (face centred orthorhombic) TiSi2 has important properties for application in electronic devices: low resistivity (16 μΩ cm), stability up to 900°C and compatibility with silicon processing. In thin films this phase is formed above approx. 700°C. However before this phase is formed, a metastable TiSi2 phase with the C49 (or ZrSi2) structure [1] is already formed at lower temperature. This C49 phase is unfavourable as metallization in IC applications because of the high resistivity (60–300 μΩ cm). From a technological point of view however it is important to realize that during the C49 formation the thin film is subject to a large change of the intrinsic stress. The occurrence of this stress can cause problems during semiconductor device fabrication. Gate oxides in MOSFETs (and other IC microstructures) may be deteriorated by stress. Also focussing problems in lithographic steps can arise because of wafer warpage. In this paper we present in situ stress measurements of the formation of TiSi2 C49 from Ti-Si multilayers. From these measurements the kinetics of the formation process is analyzed.