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The Impact of Device Asymmetry on the Electrical and Reliability Properties of Ferroelectric PZT for Memory Applications

Published online by Cambridge University Press:  15 February 2011

Jiyoung Kim ,
C. Sudhama ,
Vinay Chikarmane ,
Rajesh Khamankar ,
Jack Lee  and
Al Tasch
Jiyoung Kim
Affiliation:
Microelectronics Research Center, The University of Texas at Austin, Austin, TX78712.
C. Sudhama
Affiliation:
Microelectronics Research Center, The University of Texas at Austin, Austin, TX78712.
Vinay Chikarmane
Affiliation:
Microelectronics Research Center, The University of Texas at Austin, Austin, TX78712.
Rajesh Khamankar
Affiliation:
Microelectronics Research Center, The University of Texas at Austin, Austin, TX78712.
Jack Lee
Affiliation:
Microelectronics Research Center, The University of Texas at Austin, Austin, TX78712.
Al Tasch
Affiliation:
Microelectronics Research Center, The University of Texas at Austin, Austin, TX78712.
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Abstract

The origin and the effects of asymmetrical electrical behavior in sputtered PZT (Zr/Ti=65/35) thin film capacitors with Pt electrodes have been studied. The asymmetry and constriction in the P-E hysteresis loops are understood to result from differences in mechanical stress at the top and bottom PZT/Pt interfaces because they experience different thermal cycles during fabrication. A method for correctly positioning asymmetric loops on the polarization axis is suggested. Both d.c. and a.c. electrical stressing (of either polarity) lead to hysteresis relaxation and symmetrization. A post-processing anneal leads to electrically symmetrical devices.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 265: Symposium H – Materials Reliability in Microelectronics II , 1992 , 313
Copyright
Copyright © Materials Research Society 1992

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References

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