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Erbium-Silicided Source/Drain Junction Formation by Rapid Thermal Annealing Technique for Decananometer-Scale Schottky Barrier Metal-Oxide-Semiconductor Field- Effect Transistors
Published online by Cambridge University Press: 17 March 2011
Abstract
The stable growth conditions of erbium-silicide on silicon-on-insulator (SOI) are investigated considering annealing temperature, SOI and sputtered erbium thickness. From the sheet resistance measurement, X-ray diffraction and Auger electron spectroscopy analysis, the optimum annealing temperature is determined as 500°C. Also, for the stable growth of erbium- silicide on SOI, the sputtered erbium thickness should be less than 1.5 times of SOI thickness. As the SOI thickness decreases below this critical thickness, erbium-rich region is formed at the erbium-silicide and buried-oxide interface. By applying the optimized erbium-silicide growth conditions, 50-nm-gate-length n-type SB-MOSFET is manufactured, which shows the possible usage of erbium-silicide as the source and drain material in the n-type Schottky barrier MOSFETs for decananometer regime applications.
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- Copyright © Materials Research Society 2004