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Electromigration Testing of via Terminated Test Structures

Published online by Cambridge University Press:  10 February 2011

Kia Seng Low
Affiliation:
Infineon Technologies AG, Munich, GERMANY.Anthony O'Neill, University of Newcastle Upon Tyne, Department of Electrical and Electronic Engineering, UNITED KINGDOM.
Hans Poetzlberger
Affiliation:
Infineon Technologies AG, Munich, GERMANY.Anthony O'Neill, University of Newcastle Upon Tyne, Department of Electrical and Electronic Engineering, UNITED KINGDOM.
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Abstract

In this paper we describe three phenomena that have been observed in via terminated test structures. The first is the effect of stress voiding on the electromigration current density exponent, n. We have tested stress-voided lines and the results show that the current density exponent is close to 1. This is consistent with the prediction that stress-voided lines have a lower lifetime. We propose that the current density exponent must be measured and not assumed for such lines. The second phenomenon is the reservoir effect in via-terminated lines. Void locations following electromigration stressing are shown for a via-terminated structure containing a reservoir, prepared by Focused Ion Beam (FIB), and a discussion of the reservoir effect is presented. Finally, we report on the correlation between void location and the bimodal distribution of failure mechanisms that have been observed.

Type
Research Article
Copyright
Copyright © Materials Research Society 1999

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References

[1] Trattles, J.T., A.G. O'Neill and Mecrow, B.C., J. Appl. Phys. 75, 7799, 1994.Google Scholar
[2] Oates, A.S., Int'l Reliability Physics Symposium, 297, 1993.Google Scholar
[3] Marieb, T., Flinn, P., Bravman, J.C., Gardner, D. and Madden, M., J. Appl. Phys. 78 (2), pp. 10261032 (1995).Google Scholar
[4] Fujii, M., Koyama, K. and Aoyama, J., VLSI Multilevel Interconnection Conference, 312317, 1996.Google Scholar
[5] Kakuhara, Y., Gekkan Semiconductor World, 174, 1995.Google Scholar
[6] Kawasaki, H., Lee, C., Anderson, S.G.H.. and Pintchovski, F., Stress-Induced Phenomena in metallisation, Third Int'l Workshop, 185197, 1995.Google Scholar
[7] Filippi, R.G., Biery, G.A. and Wachnik, R.A., Stress-Induced Phenomena in metallisation, Third Int'l Workshop, 224239, 1995.Google Scholar