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Electrical breakdown in a two-layer dielectric in the MOS structure

Published online by Cambridge University Press:  28 July 2011

Xiaolong Yang
Affiliation:
NanoFAB Center and Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX 76019
Qianghua Xie
Affiliation:
Physical Analysis Laboratory, Semiconductor Products Sector, Motorola, Tempe, AZ 85284
Meng Tao
Affiliation:
NanoFAB Center and Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX 76019
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Abstract

The formation of interfacial oxide between high-k and Si creates a two-layer dielectric in the MOS structure. In this paper, we present a model to describe electrical breakdown in the two-layer dielectric. Depending on the thickness ratio of the two dielectric layers, electrical breakdown can occur either in one dielectric after the other or simultaneously. In the case of one-by-one breakdown, the current through the two-layer dielectric shows three regimes with applied voltage: tunneling through two layers, tunneling through one layer, and breakdown for both layers. Our model has been compared with experimental data obtained from the HfOx/SiO2 MOS structure, and a good agreement is achieved. This model can be used to estimate either the thickness, breakdown field, or dielectric constant of each of the two dielectric layers. It can also predict the overall breakdown voltage for different combinations of dielectric layers. When combined with C-V measurements, more information about the two-layer dielectric is obtained.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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