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Effect of Spacer Scaling on PMOS Transistors

Published online by Cambridge University Press:  01 February 2011

Wai Shing Lau ,
Chee Wee Eng ,
David Vigar ,
Lap Chan  and
Soh Yun Siah
Wai Shing Lau
Affiliation:
[email protected], Nanyang Technological University, School of EEE, NTU, School of EEE, Block S2.1, Nanyang Avenue, Singapore, Singapore, 639798, Singapore, (65) 97425167, (65) 6733318
Chee Wee Eng
Affiliation:
[email protected], Chartered Semiconductor Manufacturing Ltd, Woodlands Industrial Park D St. 2, Singapore, Singapore, 738406, Singapore
David Vigar
Affiliation:
[email protected], Chartered Semiconductor Manufacturing Ltd, Woodlands Industrial Park D St. 2, Singapore, Singapore, 738406, Singapore
Lap Chan
Affiliation:
[email protected], Chartered Semiconductor Manufacturing Ltd, Woodlands Industrial Park D St. 2, Singapore, Singapore, 738406, Singapore
Soh Yun Siah
Affiliation:
[email protected], Chartered Semiconductor Manufacturing Ltd, Woodlands Industrial Park D St. 2, Singapore, Singapore, 738406, Singapore
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Abstract

Our observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.

Keywords

electrical propertiesdevicesSi
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 913: Symposium D – Transistor Scaling – Methods, Materials and Modeling , 2006 , 0913-D03-04
Copyright
Copyright © Materials Research Society 2006

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