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Effect of Polysilicon Deposition and Thermal Cycling on Thin Oxide Quality

Published online by Cambridge University Press:  28 February 2011

N.R. Wu ,
S. Chiao ,
B. Bhushan ,
T. Batra ,
S.K. Fan ,
P. Pizzo  and
C.Y. Yang
N.R. Wu
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
S. Chiao
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
B. Bhushan
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
T. Batra
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
S.K. Fan
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
P. Pizzo
Affiliation:
Materials Engineering Department, San Jose State University, San Jose, CA 95192
C.Y. Yang
Affiliation:
EECS Department, Santa Clara University, Santa Clara, CA 95053
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Abstract

A scaled-down MOS transistor requires high-quality thin gate oxide (∼100 Å) as in tunnel oxide for an EEPROM device. Instead of investigating the lower (SiO2/Si) interface properties, we study the upper (poly-Si/SiO2) interface as affected by poly deposition conditions, phosphorus doping, and thermal cycling. The results show that prolonged or high-temperature heat treatment will degrade thin oxide quality. The initial V-t slope derived from constant-current stressing data is used to assess oxide quality.

Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 71: Symposium F – Materials Issues in Silicon Integrated Circuit Processing , 1986 , 513
Copyright
Copyright © Materials Research Society 1986

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