Hostname: page-component-586b7cd67f-t8hqh Total loading time: 0 Render date: 2024-12-03T19:01:11.034Z Has data issue: false hasContentIssue false
  • English
  • Français

Effect of Annealing Temperature on SiC Wafer Bow and Warp

Published online by Cambridge University Press:  01 February 2011

Xueping Xu  and
Chris Martin
Xueping Xu
Affiliation:
[email protected], II-VI Incorporated, Wide Bandgap Materials Group, 20 Chapin Road, Suite 1005, Pine Brook, NJ, 07058, United States
Chris Martin
Affiliation:
[email protected], II-VI Incorporated, Wide Bandgap Materials Group, 20 Chapin Road, Suite 1005, Pine Brook, NJ, 07058, United States
Get access

Abstract

Single-side polished silicon carbide wafers could exhibit large bow and warp due to the presence of mechanical damage on the unpolished surface. In this study, we investigated the effect of thermal annealing on the wafer bow. Two commercial-grade, double-side polished 3¡¨ 6H SiC wafers with the bow less than 5 μm were lapped using 12 μm diamond grit. One wafer was lapped on the C-face and another on the Si-face. The lapped wafers were subjected to annealing in vacuum at temperatures between 500¢XC and 2040¢XC. The wafer bow and x-ray rocking curves were measured prior to annealing and after each annealing step in order to evaluate the extent of the surface damage and degree of healing. Thermal annealing led to a decrease in the wafer bow and sharpening of the x-ray rocking curves. However, the wafer bow generated by lapping was not completely removed until annealing temperature reached ∼2000°C.

Keywords

x-ray diffraction (XRD)annealingcrystal growth
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1069: Symposium D – Silicon Carbide 2008—Materials, Processing and Devices , 2008 , 1069-D07-23
Copyright
Copyright © Materials Research Society 2008

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Neudeck, P. G., in The VLSI Handbook, edited by Chen, W. K. (CRC Press and IEEE Press, Boca Raton, Florida, 2000), p. 6.1–6.24 Google Scholar
2. Gupta, A. Semenas, M .E., Emorhokpor, E., Chen, J., Zwieback, I., Souzis, A. and Anderson, T., Mater. Sci. Forum Vols. 527-529 (2006), pp 43–46.Google Scholar
3. Okojie, R. S. and Zhang, M., Mat. Res. Soc. Symp. Proc. Vol. 815 (2004), pp. 133–138.Google Scholar
4..Okojie, R. S., Huang, X., Dudley, M., Zhang, M. and Pirouz, P., Mat. Res. Soc. Symp. Proc. Vol. 911 (2006), pp 145–150.Google Scholar
5. Okojie, R. S., Mater. Sci. Forum Vols. 457-460 (2004), pp 375–378.Google Scholar
6.II-VI., 20 Chapin Rd, Suite 1005. Pine Brook. NJ 07058Google Scholar
7.Calculated from formula σ=0.5EdR -1 where σ is the wafer stress, E is Young's module, d is wafer thickness and R is radius of curvature of the lapped wafer.Google Scholar
8. Yoganathan, M., Wu, P. and Zwieback, I., Mater. Sci. Forum, in press.Google Scholar
9..See, for example, Anthony, F. M., Khounsary, A. M., McCarter, D. R., Krasnicki, F. and Tangedahl, M., Proc. SPIE, Vol. 4115 (2001), pp 37–44.Google Scholar