Hostname: page-component-586b7cd67f-rcrh6 Total loading time: 0 Render date: 2024-11-23T11:12:34.258Z Has data issue: false hasContentIssue false

Dual Damascene Reactive Ion Etch Polymer Characterization through X-Ray Photoelectron Spectroscopy for 65 nm and 45nm Technology Nodes

Published online by Cambridge University Press:  31 January 2011

Samuel Choi
Affiliation:
[email protected], IBM, Research, 2070 Route 52, Hopewell Junction, New York, 12533, United States, 8458923613
Chet Dziobkowski
Affiliation:
[email protected], IBM Microelectronics SRDC, Hopewell Junction,, New York, United States
Leo Tai
Affiliation:
[email protected], IBM Microelectronics SRDC, Hopewell Junction,, New York, United States
Get access

Abstract

At 65nm and beyond technology nodes, copper interconnect formation in dual damascene integration is continually challenged from a polymer management perspective. Highly polymeric plasma chemistry is required to reduce line edge roughness, shape physical profile, and control critical dimension across a 300mm wafer. But too much fluorocarbon deposition on a wafer results in poor defects yield.

In this paper, X-ray photoelectron spectroscopy (XPS) characterization technique is used to quantify and to optimize a metal line reactive ion etch process to increase electrical opens yield. A reduction of 2 at.% in carbon mass results in a Do (defects/cm2) improvement from > 2.0 to less than 1.0. This result is realized without a shift to the trench physical profile which is important for reliability performance. Moreover, with a shorter turnaround time of XPS characterization compared to electrical hardware splits, quicker yield learning cycle is realized for both RIE process and module integration.

Type
Research Article
Copyright
Copyright © Materials Research Society 2009

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1 Edelstein, D. C., Sai-Halasz, G. A., Mii, Y.-J., “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Research and Development Vol. 39, No. 4 (1995).Google Scholar
2 Dalton, T. J., Fuller, N., Gibson, G., Kumar, K., “Dielectric Etching Technology ReviewAmerican Vacuum Society Conference PS-TuA1 4 Nov (2003).Google Scholar
3 Kumar, K., “Plasma-Lithography Interactions for Advanced CMOS Manufacturing (45nm and Beyond)AVS, October 2008.Google Scholar
4Tool description and fundamentals of XPS http://www.phi.com/techniques/xps.html Google Scholar
5 Ciplickas, Dennis J., et al. “Advanced Yield Learning Through Predictive Micro-Yield Modeling” Proc. 7th IEEE/ISSM, Oct. 1998.Google Scholar