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Dual Damascene Process for FatWires in Copper/FSG Technology

Published online by Cambridge University Press:  01 February 2011

J. Gambino
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
T. Stamper
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
H. Trombley
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
S. Luce
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
F. Allen
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
C. Weinstein
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
B. Reuter
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
M. Dunbar
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
V. Samek
Affiliation:
IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452
P. McLaughlin
Affiliation:
IBM Microelectronics, 1580 Route 52, Hopewell Junction, NY 12533
T. Kane
Affiliation:
IBM Microelectronics, 1580 Route 52, Hopewell Junction, NY 12533
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Abstract

A trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

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