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Dry Etching for Nanometer-Scale Fabrication

Published online by Cambridge University Press:  21 February 2011

Richard E. Howard
Richard E. Howard*
Affiliation:
AT&T Bell Laboratories Room 4E-332 Holmdel, NJ 07733
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Abstract

Conventional integrated circuit fabrication is currently making the transition from wet to dry etching in the effort to shrink feature sizes to about 1 micron. These plasma etching techniques, though, are not limited to micron dimensions; devices and structures smaller than 100 nm can be made. Using e-beam lithography and reactive ion etching, patterns down to about 20 nm have been made in tri-level stencils and in semiconductor substrates. Working silicon MOSFETs with gate widths down to about 30 nm have also been made. These MOSFET devices are so small that individual electron trapping events can be observed. These devices are being studied to give a better understanding of the physics of electronic conduction in small devices and better define the limits of microfabrication.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 38: Symposium F – Plasma Synthesis and Etching of Electronic Materials , 1984 , 247
Copyright
Copyright © Materials Research Society 1985

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References

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