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Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors

Published online by Cambridge University Press:  01 February 2011

Nihar Ranjan Mohapatra ,
Souvik Mahapatra  and
V. Ramgopal Rao
Nihar Ranjan Mohapatra
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India.
Souvik Mahapatra
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India.
V. Ramgopal Rao
Affiliation:
Department of Electrical Engineering Indian Institute of Technology, Bombay, 400 076, India.
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Abstract

This paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier injection mechanism. The degradation mechanism is studied for different values of substrate voltage over a wide range of channel length and oxide thickness. Stress and charge pumping measurements are carried out to study the degradation under identical bias (gate, drain, substrate) and gate current condition. The influence of device dimensions on the gate injection efficiency and hot carrier degradation is also studied. Results show that the degradation under negative substrate voltage operation is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanism responsible for such trends is discussed. It is also found that, under identical gate current (programming time in flash memory cells), the degradation is less for higher negative substrate bias, which is helpful in realizing fast and reliable flash memories.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 716: Symposium B – Silicon Materials-Processing, Characterization, and Reliability , 2002 , B7.2
Copyright
Copyright © Materials Research Society 2002

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