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Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

Published online by Cambridge University Press:  26 February 2011

Ronald J. Gutmann ,
J. Jay McMahon  and
Jian-Qiang Lu
Ronald J. Gutmann
Affiliation:
[email protected], RPI, CIE, 6015 CII, 110 8th st, Troy, NY, 12180, United States
J. Jay McMahon
Affiliation:
[email protected], Rensselaer Polytechnic Institute, Center for Integrated Electronics, CII 6015, 110 8th St, Troy, NY, 12180, United States
Jian-Qiang Lu
Affiliation:
[email protected], Rensselaer Polytechnic Institute, Center for Integrated Electronics, CII 6015, 110 8th St, Troy, NY, 12180, United States
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Abstract

A monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

Keywords

adhesivebondingmetal
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y04-02
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

1. Chen, K. N., Tan, C. S., Fan, A., and Reif, R., “Morphology and Bond Strength of Copper Wafer Bonding”, Electrochemical and Solid State Letters, Vol. 7, No. 1, pp. G14–G16, 2004.Google Scholar
2. Chen, K., Fan, A., and Reif, R., “Interfacial Morphologies and Possible Mechanisms of Copper Wafer Bonding”, Journal of Materials Science, Vol. 37, pp. 3441–3446, 2002.Google Scholar
3. Chen, K. N., Tan, C. S., and Reif, R., “Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in Three-Dimensional Integration During Current Stressing”, Applied Physics Letters, Vol. 86, No. 011903, pp. 011903–1, 2005.Google Scholar
4. Gutmann, R. J., Lu, J.-Q., Kwon, Y., McDonald, J. F., and Cale, T. S., “Three-Dimensional (3D) ICs: A Technology Platform for Integrated Systems and Opportunities for New Polymeric Adhesives”, IEEE Polytech, pp. 173–180, 2001.Google Scholar
5. Lu, J.-Q., Jindal, A., Kwon, Y., McMahon, J., Cale, T.S., and Gutmann, R.J., “Evaluation Procedures for Wafer Bonding and Thinning with Interconnect Test Structures for 3D ICs”, in Proceedings of International Interconnect Technology Conference, pp. 74–76, 2003.Google Scholar
6. Gutmann, R.J., Lu, J.-Q., Pozder, S., Kwon, Y., Menke, D., Jindal, A., Celik, M., Rasco, M., McMahon, J.J., Yu, K. and Cale, T.S., “A Wafer-Level 3D IC Technology Platform”, in Proceedings of Advanced Metallization Conference, pp. 19–26, 2003.Google Scholar
7. Patti, R., “Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs”, Proceedings of the IEEE, Vol. 94, No. 6, pp. 1214–1222, 2006.Google Scholar
8. Gupta, S., Hilbert, M., Hong, S., and Patti, R., “Techniques For Producing 3D ICs With High-Density Interconnect”, In Proceedings of 2004 VLSI Multilevel Interconnection Conference, pp. 93–97, 2004.Google Scholar
9. Morrow, P., Kobrinsky, M. J., Ramanathan, S., Park, C.-M., Harmes, M., Ramachandrarao, V., Park, H.-M., Kloster, G., List, S., and Kim, S., “Wafer Level 3D Interconnects Via Cu Bonding”, Advanced Metalization Conference 2004, pp 125–130, 2004.Google Scholar
10. Morrow, P., Park, C.-M., Ramanathan, S., Kobrinsky, M. J., and Harmes, M., “Three-Dimensional Wafer Stacking Via Cu-Cu Bonding integrated With 65-nm Strained-Si/Low-k CMOS Technology”, IEEE Electron Device Letters, Vol. 27, No. 5, pp. 335–337, 2006.Google Scholar
11. Niklaus, F., Andersson, H., Enoksson, P., and Stemme, G., “Low Temperature Full Wafer Adhesive Bonding of Structured Wafers”, Sensors and Actuators A, Vol. 92, pp. 235–241, 2001.Google Scholar
12. Niklaus, F., Stemme, G., Lu, J.-Q., and Gutmann, R. J., “Adhesive Wafer Bonding”, Journal of Applied Physics, Vol. 99, pp.031101–1, 2006.Google Scholar
13. Pandojirao-Sunkojirao, P., Dewan, R., Zhang, P., Popa, D., Chiao, J.-C., Stephanou, H. E., “Electrical Interconnects for 3D Wafer Stacks”, Proceedings of the IMAPS Device Packaging Meeting, 2006.Google Scholar
14. Pandojirao-Sunkojirao, P., Dewan, R., Zhang, P., Popa, D., Chiao, J.-C., Stephanou, H. E., “Electrical Interconnects for 3D Wafer Stacks”, Proceedings of the IMAPS Meeting, 2006.Google Scholar
15. Shigetou, A., Itoh, T., Matsuo, M., Hayasaka, N., Okumura, K., and Suga, T., “Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding Method”, IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, pp. 218–226, 2006.Google Scholar
16. McMahon, J. J., Lu, J.-Q., and Gutmann, R. J., “Wafer Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers for Via-First 3D Interconnect”, In Proceedings of the IEEE Electronic Components and Technology Conference, pp. 331–336, 2005.Google Scholar
17. Jindal, A., Lu, J.-Q., Kwon, Y., Rajagopalan, G., McMahon, J. J., Zeng, A. Y., Flesher, H. K., Cale, T. S., and Gutmann, R. J., “Wafer Thinning for Monolithic 3D Interconnects”, In Materials, Technology, and Reliability of Advanced Interconnect, MRS Symposium Proceedings, Vol. 766, pp. 21–26, 2003.Google Scholar
18. McMahon, J. J., Niklaus, F., Kumar, R. J., Yu, J., Lu, J.-Q., and Gutmann, R. J., “CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process”, Materials Research Society Symposium Proceedings, Vol. 867, pp. W4.4.1-W4.4.6, 2005.Google Scholar
19. McMahon, J. J., Kumar, R. J., Niklaus, F., Lee, S. H., Yu, J., Lu, J.-Q., and Gutmann, R. J., “Unit Processes for Cu/BCB Redistribution Layer Bonding for 3D ICs”, In Proceedings of the Advanced Metalization Conference, pp. 179–183, 2005.Google Scholar
20. Gutmann, R. J., McMahon, J. J., Rao, S., Niklaus, F., and Lu, J.-Q., “Wafer-Level Via-First 3D Integration With Hybrid-Bonding of Cu/BCB Redistribution Layers”, Proceedings of the International Wafer Level Packaging Congress, 2005.Google Scholar
21. Chen, K. N., Tan, C. S., Fan, A., and Rief, R., “Morphology and bond strength of copper wafer bonding”, Electrochemical and Solid State Letters, Vol. 7, No. 1, pp. G14–G16, 2004.Google Scholar
22. Chen, K. N., Fan, A., and Rief, R., “Microstructure Examination of Copper Wafer Bonding”, Journal of Electronic Materials, Vol. 30, No. 4, pp. 331–335, 2001.Google Scholar
23. Chen, K. N., Tan, C. S., and Reif, R., “Abnormal contact resistance reduction of bonded copper interconnects in three-dimensional integration during current stressing”, Applied Physics Letters, Vol. 86, No. 011903, pp. 011903–1, 2005.Google Scholar
24. Gutmann, R. J., McMahon, J. J., and Lu, J.-Q., “Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs” (invited), World Tribology Congress III, Washington D.C., 2005.Google Scholar
25. McMahon, J. J., Lu, J.-Q., and Gutmann, R. J., “Three Dimensional (3D) Integration”, in “Microelectronic Applications of Chemical Mechanical Planarization”, Yuzhuo Li, John Wiley and Sons, New York, N.Y. (in press).Google Scholar