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Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer”

Published online by Cambridge University Press:  26 February 2011

Manabu Bonkohara ,
Makoto Motoyoshi ,
Kazutoshi Kamibayashi  and
Mitsumasa Koyanagi
Manabu Bonkohara
Affiliation:
[email protected], ZyCube Co.,Ltd., Headquaters, Mitsuyoshi Bldg. 9F, 3-5-13 Nihonbashi,Chuo-ku, Japan, Tokyo, 103-0027, Japan, +81-3-6202-9690, +81-3-6202-9691
Makoto Motoyoshi
Affiliation:
[email protected], ZyCube Co., Ltd., Tokyo, 103-0027, Japan
Kazutoshi Kamibayashi
Affiliation:
[email protected], ZyCube Co., Ltd., Tokyo, 103-0027, Japan
Mitsumasa Koyanagi
Affiliation:
[email protected], Tohoku University, Sendai, 980-0845, Japan
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Abstract

Recently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is taken our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are the five key technologies are described. And considering con and pro of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer), We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

Keywords

packagingsensorself-assembly
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y03-03
Copyright
Copyright © Materials Research Society 2007

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References

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