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Control of Stress in Surface Engineered Silicon
Published online by Cambridge University Press: 01 February 2011
Abstract
Hydrogen plasma (H-plasma) treatments applied on (100)-oriented standard Czochralski (Cz) silicon wafers cause a structuring of the surface regions in the sub-100 nm scale. The reconstruction of the ‘nano-structured’ surface layers by high temperature vacuum annealing induces strong tensile stress (∼ GPa) at the surface and in the subsurface regions of the wafers, as can be verified by depth resolved μ-Raman spectroscopy (μRS). Although the H-plasma caused ‘nano-structured’ surface layer is very thin (100 – 200 nm), the stressed subsurface regions of the annealed samples are quite extended, i.e. up to ∼ 10 μm depth. The impacts of several process parameters including 1) the doping type of the wafer substrate, 2) the frequency of the H-plasma, 3) the power and duration of the H-plasma, 4) the temperature and duration of the vacuum annealing on the stress are investigated. It is found that the stressed region in the surface engineered silicon wafer can be controlled by the process parameters. The presented results might be important for various applications in semiconductor technology. For example, the H-plasma exposure could be done in local areas near the electrically active regions on the forefront of the wafer. After appropriate annealing, stressed local regions for external getter purposes can be created. Such a method might especially be useful for the formation of getter regions on SOI substrates.
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- Copyright © Materials Research Society 2005