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Advanced Ion Implantation Technology for High Performance Transistors

Published online by Cambridge University Press:  21 March 2011

Kyoichi Suguro ,
Atsushi Murakoshi ,
Toshihiko Iinuma ,
Haruko Akutsu ,
Takeshi Shibata ,
Yoshikazu Sugihara  and
Katsuya Okumura
Kyoichi Suguro
Affiliation:
TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan, Phone: +81-45-770-3663, •• Fax: +81-45-770-3577, [email protected]
Atsushi Murakoshi
Affiliation:
TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan, Phone: +81-45-770-3663, •• Fax: +81-45-770-3577
Toshihiko Iinuma
Affiliation:
TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan, Phone: +81-45-770-3663, •• Fax: +81-45-770-3577
Haruko Akutsu
Affiliation:
TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan, Phone: +81-45-770-3663, •• Fax: +81-45-770-3577
Takeshi Shibata
Affiliation:
TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan, Phone: +81-45-770-3663, •• Fax: +81-45-770-3577
Yoshikazu Sugihara
Affiliation:
TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan, Phone: +81-45-770-3663, •• Fax: +81-45-770-3577
Katsuya Okumura
Affiliation:
TOSHIBA CORPORATION, Process & Manufacturing Eng. Center, Semiconductor Company, TOSHIBA Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan, Phone: +81-45-770-3663, •• Fax: +81-45-770-3577
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Abstract

Cryo-implantation technology is proposed for reducing crystal defects in Si substrates. The substrate temperature was controlled to be below at -160°C during ion implantation. No dislocation was observed in the implanted layer after rapid thermal annealing. Pn junction leakage was successfully reduced by one order of magnitude as compared with room temperature implantation. Precise dose control is indispensable in channel region of high performance MOSFETs. In order to improve the precision of implanted dose, chip size implantation technology without photoresist mask was developed. In this technology, chip-by-chip implantation can be carried out by step-and-repeat wafer stage, and different implantation conditions are available in the same wafer independent of wafer size.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 669: Symposium J – Si Front-End Processing–Physics and Technology of Dopant-Defect Interactions III , 2001 , J1.3
Copyright
Copyright © Materials Research Society 2001

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References

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