The increasing demands of miniaturization in the microelectronics industry has forced continual improvement in the materials that are used in the fabrication of semiconductor devices. Advances in photoresists for microlithographic applications have reduced the feature size to 0.25 µm and below, and this drive to eversmaller features, coupled with the introduction of copper, has placed increasing demands on the dielectric material. Materials with lower dielectric constants (depicted in dark gray in Figure 1) are therefore required to more efficiently insulate these submicron features, such as the copper interconnect lines used to connect the transistors and memory cells in these advanced multilevel devices (Figure 1). This allows the minimization of crosstalk, signal delays, and power consumption. While vapor-deposited silicon dioxide and other derivatives are currently being employed, they suffer from unacceptably high dielectric constants (ε > 3.6) and are unacceptable for future generations of microelectronic devices.