Hostname: page-component-cd9895bd7-p9bg8 Total loading time: 0 Render date: 2024-12-24T17:32:06.841Z Has data issue: false hasContentIssue false
  • English
  • Français

Gate contact materials in Si channel devices

Published online by Cambridge University Press:  18 February 2011

Huang-Chun Wen  and
J.J. Chambers
Huang-Chun Wen
Affiliation:
Texas Instruments; [email protected]
J.J. Chambers
Affiliation:
Texas Instruments; [email protected]
Get access

Abstract

Research on contact materials in silicon semiconductor devices has recently gained significant momentum due to the increasing performance demands as the complementary metal oxide semiconductor technology advances. Applications include transistor materials such as gate electrodes and contacts to highly doped semiconductors substrates. This review will discuss the key issues in the development of metal gate electrodes with high-κ dielectrics to replace the conventional polycrystalline silicon electrode. Challenges in establishing a work function measurement technique, the role of the metal/high-κ interface in modulating the effective work function, and a review of leading industry solutions will be discussed.

Type
Research Article
Information
MRS Bulletin , Volume 36 , Issue 2: Contact materials for nanoelectronics , February 2011 , pp. 101 - 105
Copyright
Copyright © Materials Research Society 2011

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1.Moore, G.E., “Progress in digital integrated electronics,” presented at Electron Devices Meeting, International, 1975.Google Scholar
2.Lee, B.H. et al. , “Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application,” presented at Electron Devices Meeting, 1999. IEDM Technical Digest, International, 1999.Google Scholar
3.Wilk, G.D., Wallace, R.M., Anthony, J.M., Journal of Applied Physics 89, 5243 (2001).CrossRefGoogle Scholar
4.Hobbs, C., Fonseca, L., Dhandapani, V., Samavedam, S., Taylor, B., Grant, G., Dip, L., Triyoso, D., VLSI Technology Digest, 9–10 (2003).Google Scholar
5.Yeo, Y.C., Ranade, P., King, T.J., Hu, C.M., Journal of Applied Physics 92, 7266 (2002).CrossRefGoogle Scholar
6.Wong, C.Y. et al. , “Doping of n+ and p+ polysilicon in a dual-gate CMOS process,” presented at Electron Devices Meeting, 2003.Google Scholar
7.Hu, J.C., Yang, H., Kraft, R., Rotondaro, A.L.P., Hattangady, S., Lee, W.W., Chapman, R.A., Chao, C.-P., Chatterjee, A., Hanratty, M., Rodder, M., Chen, I.-C., “Feasibility of using W/TiN as metal gate for conventional 0.13 μm CMOS technology and beyond,” Electron Devices Meeting, 1997. Technical Digest, International, 825 (1997).Google Scholar
8.Chudzik, M., Doris, B., Mo, R., Sleight, J., Cartier, E., “High-performance high-k/metal gates for 45 nm CMOS and beyond with gate-first processing,” VLSI, 194, 2007.CrossRefGoogle Scholar
9.Chen, X., et al. , “A cost effective 32 nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process,” VLSI, 88, 2008.CrossRefGoogle Scholar
10.Arnaud, F., et al. , “32 nm general purpose bulk CMOS technology for high performance applications at low voltage,” IEDM, 633 (2008).CrossRefGoogle Scholar
11.Mistry, K., et al. , “A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging,” IEDM, 247, 2007.CrossRefGoogle Scholar
12.Packan, P., et al. , “High performance 32 nm logic technology featuring 2nd generation high-k + metal gate transistors,” IEDM, 659, 2009.CrossRefGoogle Scholar
13.Jan, C.H., et al. , “A 32 nm SoC Platform Technology With 2nd Generation High-k/Metal Gate Transistorspp,” IEDM, 647, 2009.Google Scholar
14.Michaelson, H., Journal of Applied Physics 48, 4729 (1977).CrossRefGoogle Scholar
15.Wen, H.C. et al. . IEEE Electron Device Letters, 27, 598–601 (2006).CrossRefGoogle Scholar
16.Brown, G. et al. , “An Improved Methodology for Gate Electrode Work Function Extraction in SiO2 and High-k Gate Stack Systems Using Terraced Oxide Structures,” IEEE SISC conference, 2004.Google Scholar
17.Wen, H.C. et al. , “Work function engineering of RuHf alloys as gate electrodes for future generation dual metal CMOS,” presented at VLSI Technology, 2005.Google Scholar
18.Wen, H.C., PhD dissertation, The University of Texas at Austin, pp. 61, 130 (2006).Google Scholar
19.Wen, H.C., Lysaght, P., Alshareef, H.N., Huffman, C., Harris, H.R., Choi, K., Senzaki, Y., Luan, H., Majhi, P., Lee, B.H., Campin, M.J., Foran, B., Lian, G.D., Kwong, D.-L., Journal of Applied Physics 98, 043520 (2005).CrossRefGoogle Scholar
20.Wen, H.-C., Choi, K., Lysaght, P., Majhi, P., Alshareef, H., Huffman, C., Harris, R., Luan, H., Lee, B.H., Yamada, N., presented at VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on pp. 107–108, 2005.Google Scholar
21.Sim, J.H., et al. , Electron Device Letters, IEEE, 24, 631 (2003).CrossRefGoogle Scholar
22.Wen, H.C., et al. , VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium, 46 (2005).Google Scholar
23.Wen, H.C.. et al. , VLSI Technology, 2007. Digest of Technical Papers. 2007 Symposium, 160 (2007).Google Scholar
24.Wen, H.C., Microelectronic Engineering 85, 2 (2008).CrossRefGoogle Scholar
25.Alshareef, H.N. et al. , Future Fab 19, 91 (2006).Google Scholar
26.Alshareef, H.N., Luan, H.F., Choi, K., Harris, H.R., Wen, H.C., Quevedo-Lopez, M.A., Majhi, P., Lee, B.H., Applied Physics Letters 88, 112114 (2006).CrossRefGoogle Scholar
27.Kirsch, P.D. et al. , Applied Physics Letters 92, 092901 (2008).CrossRefGoogle Scholar
28.Hinkle, C. et al. , “Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt,” VLSI Symp 2010 17.3.CrossRefGoogle Scholar
29.Song, S.C. et al. , “Mechanism of VFB roll-off with high work function metal gate and low temperature oxygen incorporation to achieve PMOS band edge work function,” Electron Devices Meeting, 2007. IEDM 2007. IEEE International.CrossRefGoogle Scholar
30.Hinkle, C., Galatage, R.V., Chapman, R.A., Vogel, E.M., Alshareef, H.N., Freeman, C., Wimmer, E., Niimi, H., Li-Fatou, A., Shaw, J.B., Chambers, J.J., Applied Physics Letters 96, 103502 (2010).CrossRefGoogle Scholar
31.Bersuker, G., Park, C.S., Wen, H.C., Choi, K., Sharia, O, O., Demkov, A., “Origin of the flat-band voltage (VFB) roll-off phenomenon in metal/high-k gate stacks” ESSDERC 2008.Google Scholar
32.Tatsumura, K. et al. , “Intrinsic Correlation between Mobility Reduction and Vt shift due to Interface Dipole Modulation in HfSiON/SiO2 stack by La or Al addition,” in IEDM Technical Digest, IEDM, p. 25 (2008).Google Scholar