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Strain scaling for CMOS

Published online by Cambridge University Press:  12 February 2014

S.W. Bedell ,
A. Khakifirooz  and
D.K. Sadana
S.W. Bedell
Affiliation:
IBM T.J. Watson Research Center; [email protected]
A. Khakifirooz
Affiliation:
IBM T.J. Watson Research Center; [email protected]
D.K. Sadana
Affiliation:
IBM T.J. Watson Research Center; [email protected]
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Abstract

This article describes various techniques for applying strain to current and future complementary metal–oxide–semiconductor (CMOS) channels to boost CMOS performance. A brief history of both biaxial and uniaxial strain engineering in planar CMOS technology is discussed. Scalability challenges associated with process-induced uniaxial strain in sub-22 nm CMOS is highlighted in view of shrinking device dimensions and 3D device architecture (such as fin field-effect transistors [FinFETs]). Non-uniform strain relaxation in patterned geometries in tight pitch two- and three-dimensional devices is addressed. A case is made that the future scalable strain platform will require a combination of biaxial strain at wafer level in conjunction with local uniaxial strain. Finally, potential application of strain engineering to advanced III–V metal oxide semiconductor FET channels will be examined.

Keywords

III-Vmicroelectronicssiliconstress/strain relationshipsemiconducting
Type
Research Article
Information
MRS Bulletin , Volume 39 , Issue 2: Elastic Strain Engineering , February 2014 , pp. 131 - 137
Copyright
Copyright © Materials Research Society 2014 

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