Hostname: page-component-745bb68f8f-b95js Total loading time: 0 Render date: 2025-01-10T15:11:04.655Z Has data issue: false hasContentIssue false
  • English
  • Français

Applications of three-dimensional LSI

Published online by Cambridge University Press:  10 March 2015

Mitsumasa Koyanagi ,
Takafumi Fukushima ,
Kang-Wook Lee  and
Tetsu Tanaka
Mitsumasa Koyanagi
Affiliation:
Tohoku University, Japan; [email protected]
Takafumi Fukushima
Affiliation:
New Industry Creation Hatchery Center, Tohoku University, Japan; [email protected]
Kang-Wook Lee
Affiliation:
New Industry Creation Hatchery Center, Tohoku University, Japan; [email protected]
Tetsu Tanaka
Affiliation:
Tohoku University, Japan; [email protected]
Get access

Abstract

To overcome various concerns due to scaling-down device size in future large-scale integration (LSI), it is indispensable to introduce a new concept of heterogeneous three-dimensional (3D) integration in which various kinds of device chips with different sizes, devices, and materials are vertically stacked. To achieve such heterogeneous 3D integration, the key technology of self-assembly and electrostatic (SAE) bonding has been developed. The heterogeneous 3D integration technology with the SAE bonding method has enabled 3D heterogeneous stacking of different types of chips such as the compound semiconductor device chip, photonic device chip, and spintronic device chip on complementary metal oxide semiconductor chips. A 3D image sensor with extremely fast processing speed and a 3D microprocessor with a self-test and self-repair function for future automatic driving vehicles are typical examples of heterogeneous 3D LSIs which we fabricated by the SAE bonding method.

Keywords

Self-assemblybondingpolymerreactive ion etchingsputtering
Type
Research Article
Information
MRS Bulletin , Volume 40 , Issue 3: Materials challenges in 3D IC technology , March 2015 , pp. 242 - 247
Copyright
Copyright © Materials Research Society 2015 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Bohr, M., IEEE IEDM Tech. Dig. 1–4 (2011).Google Scholar
Fukushima, T., Yamada, Y., Kikuchi, H., Koyanagi, M., IEEE IEDM Tech. Dig. 359 (2005).Google Scholar
Stankovic, J.A., IEEE Internet of Things Journal 1, 3 (2014).Google Scholar
Koyanagi, M., IEEE IEDM Tech. Dig. 8 (2013).Google Scholar
Beyne, E., 3D Forum, IEEE Int. Solid-State Circuits Conf., F6 (2014).Google Scholar
Lee, K.-W., Hashimoto, H., Onishi, M., Konno, S., Sato, Y., Nagai, C., Bea, J.-C., Murugesan, M., Fukushima, T., Tanaka, T., Koyanagi, M., IEEE IEDM Tech. Dig. 669 (2014).Google Scholar
Kang, U., Chung, H.-J., Heo, S., Ahn, S.-H., Lee, H., Cha, S.-H., Ahn, J., Kwon, D.M., Kim, J.H., Lee, J.-W., Joo, H.-S., Kim, W.-S., Kim, H.-K., Lee, E.-M., Kim, S.-R., Ma, K.-H., Jang, D.-H., Kim, N.-S., Choi, M.-S., Oh, S.-J., Lee, J.-B., Jung, T.-K., Yoo, J.-H., Kim, C., IEEE Int. Solid-State Circuits Conf. Tech. Paper 130 (2009).Google Scholar
Kim, J.-S., Oh, C.S., Lee, H., Lee, D., Hwang, H.-R., Hwang, S., Na, B., Moon, J., Kim, J.-G., Park, H., Ryu, J.-W., Park, K., Kang, S.-K., Kim, S.-Y., Kim, H., Bang, J.-M., Cho, H., Jang, M., Han, C., Lee, J.-B., Kyung, K., Choi, J.-S., Jun, Y.-H., IEEE Int. Solid-State Circuits Conf. Tech. Paper, 496 (2011).Google Scholar
Jeddeloh, J., Keeth, B., IEEE Symposium on VLSI Technology, 87–88 (2012).Google Scholar
Suh, M., 3-D Architectures for Semiconductor Integration and Packaging Symp. (San Francisco, CA, December 2012).Google Scholar
Fernández-Bolaños, M., Ionescu, A.M., IEEE Intl. 3D Systems Integration Conference 1–19 (Munich, Germany, 2010).Google Scholar
Taklo, M.M.V., Ramm, P., Fleischer, M., Ionescu, A., Pufall, R., IEEE Intl. 3D Systems Integration Conference (San Francisco, CA, 2013).Google Scholar
Lee, K.-W., Noriki, A., Kiyoyama, K., Fukushima, T., Tanaka, T., Koyanagi, M., IEEE Trans. Electron Devices 58 (3), 748 (2011).Google Scholar
Tanaka, T., Kino, H., Nakazawa, R., Kiyoyama, K., Ohno, H., Koyanagi, M., IEEE Symposium on VLSI Technology and Circuits, 169–170 (2012).Google Scholar
Lee, K.-W., Noriki, A., Kiyoyama, K., Kanno, S., Kobayashi, R., Jeong, W.-C., Bea, J.-C., Fukushima, T., Tanaka, T., Koyanagi, M., IEEE IEDM Tech. Dig. 531 (2009).Google Scholar
Noriki, A., Lee, K.-W., Bea, J., Fukushima, T., Tanaka, T., Koyanagi, M., IEEE Electron Device Lett. 33 (2), 221 (2012).CrossRefGoogle Scholar
Deguchi, J., Watanabe, T., Nakamura, T., Nakagawa, Y., Fukushima, T., Shim, J.-C., Kurino, H., Koyanagi, M., Jpn. J. Appl. Phys. 43 (4B), 1685 (2004).Google Scholar
Fukushima, T., Kikuchi, H., Yamada, Y., Konno, T., Liang, J., Sasaki, K., Inamura, K., Tanaka, T., Koyanagi, M., IEEE IEDM Tech. Dig. 985–988 (2007).Google Scholar
Fukushima, T., Iwata, E., Ohara, Y., Noriki, A., Inamura, K., Lee, K.-W., Bea, J., Tanaka, T., Koyanagi, M., IEEE IEDM Tech. Dig. 349–352 (2009).Google Scholar
Fukushima, T., Hashiguchi, H., Bea, J., Ohara, Y., Murugesan, M., Lee, K.-W., Tanaka, T., Koyanagi, M., IEEE IEDM Tech. Dig. 789–792 (2012).Google Scholar
Lee, K.-W., Ohara, Y., Kiyoyama, K., Konno, S., Sato, Y., Watanabe, S., Yabata, A., Kamada, T., Bea, J.-C., Hashimoto, H., Murugesan, M., Fukushima, T., Tanaka, T., Koyanagi, M., IEEE IEDM Tech. Dig. 785–788 (2012).Google Scholar
Koyanagi, M., 3D Forum, Intl. Solid-State Circuits Conference, F1 (San Francisco, CA, 2014).Google Scholar