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Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron

Published online by Cambridge University Press:  08 June 2018

S. Dutta
Affiliation:
Indian Institute of Technology Bombay
T. Chavan
Affiliation:
Indian Institute of Technology Bombay
S. Shukla
Affiliation:
Indian Institute of Technology Bombay
V. Kumar
Affiliation:
Indian Institute of Technology Bombay
A. Shukla
Affiliation:
Indian Institute of Technology Bombay
N. Mohapatra
Affiliation:
Indian Institute of Technology Gandhinagar
U. Ganguly*
Affiliation:
Indian Institute of Technology Bombay
*
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Abstract:

Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.

Type
Articles
Copyright
Copyright © Materials Research Society 2018 

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References

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